DS2433S+ Maxim Integrated Products, DS2433S+ Datasheet
DS2433S+
Specifications of DS2433S+
Related parts for DS2433S+
DS2433S+ Summary of contents
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... Ground 5, 6 — — NC PIN CONFIGURATIONS TOP VIEW Pin Configurations continued at end of data sheet. ORDERING INFORMATION PART DS2433+ DS2433S+ DS2433S+T&R DS2433G+T&R Flip SFN DS2433X#T Chip Data Ground DS2433X-S#T Ground Data +Denotes a lead(Pb)-free package. — NC #Denotes a RoHS-compliant device that may include lead(Pb) that is — ...
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... PARASITE POWER The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power whenever the I/O input is high. I/O will provide sufficient power as long as the specified timing and voltage requirements are met. 1-Wire is a registered trademark of Maxim Integrated Products, Inc ...
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... Shifting in the eight bits of CRC should return the shift register to all zeros. MEMORY The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages called memory. The DS2433 contains pages 0 through 15 that make up the 4096-bit EEPROM. The scratch-pad is an additional page that acts as a buffer when writing to memory ...
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PF bit. Bit 6 has no function; it always reads 0. Note that the lowest five bits of the target address also determine the address within the scratchpad, where intermediate storage of data will begin. This address is called ...
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Figure 2. HIERARCHCAL STRUCTURE FOR 1-Wire PROTOCOL Figure 3. 64-BIT LASERED ROM MSB 8-BIT CRC CODE MSB Figure 4. 1-Wire CRC GENERATOR STAGE STAGE STAGE 48-BIT SERIAL NUMBER ...
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... CRC generated by the DS2433. The memory address range of the DS2433 is 0000h to 01FFh. If the bus master sends a target address higher than this, the internal circuitry of the chip will set the seven most significant address bits to zero as they are shifted into the internal address register ...
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... After the two bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 1s will be read important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected ...
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... Figure 7. MEMORY FUNCTION FLOWCHART ...
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... Figure 7. MEMORY FUNCTION FLOWCHART (continued ...
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... MEMORY FUNCTION EXAMPLE Example: Write two data bytes to memory location 0026 and 0027. Read entire memory. MASTER MODE DATA (LSB FIRST <2 data bytes> <2 data bytes> <idle or strong pullup> Reset Reset Pulse (480s to 960s) Presence Presence Pulse CCh ...
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... Speed) or more than 120s (regular speed), one or more devices on the bus may be reset. TRANSACTION SEQUENCE The protocol for accessing the DS2433 via the 1-Wire port is as follows: Initialization ROM Function Command Memory Function Command Transaction/Data WHILE THE DEVICE COPIES THE SCRATCHPAD TO EEPROM. DEPENDING ON THE 1-Wire ...
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... This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open-drain pulldowns will produce a wired-AND result) ...
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... OVERDRIVE SKIP ROM [3Ch single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive Skip ROM sets the DS2433 in the Overdrive Mode (OD = 1). All communication following this command has to occur at Overdrive Speed until a Reset Pulse of minimum 480 ...
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Figure 9. ROM FUNCTIONS FLOWCHART (FIRST PART ...
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Figure 9. ROM FUNCTIONS FLOWCHART (SECOND PART ...
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... The initialization sequence required to begin any communication with the DS2433 is shown in Figure 10. A Reset Pulse followed by a Presence Pulse indicates the DS2433 is ready to send or receive data given the correct ROM command and memory function command. The bus master transmits (Tx) a Reset Pulse (t , minimum 480 ...
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Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSES *IN ORDER NOT TO MASK INTERRUPT SIGNALLING BY OTHER DEVICES ON THE 1-WIRE BUS, t **INCLUDES RECOVERY TIME SHOULD ALWAYS BE LESS THAN 960µs. RSTL ...
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Figure 11. READ/WRITE TIMING DIAGRAM ...
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... The data may start at any location within the scratchpad. For more details on generating CRC values including example implementations in both hardware and software, refer to the Book of iButton Standards. Figure 12. CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL iButton is a registered trademark of Maxim Integrated Products, Inc ...
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ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground ..................................................................... -0.5V to +7.0V Operating Temperature Range ...............................................................................................-40C to +85C Storage Temperature Range ................................................................................................-55C to +125C Lead Temperature (PR-35, SOIC only, soldering 10s) ..................................................................... +300°C Soldering Temperature (reflow) PR-35, ...
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... PUP normal communications. 7) During the execution of the Copy Scratchpad command the DS2433 automatically erases the memory locations to be written to. No extra steps need to be taken by the bus master. 8) The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value ...
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PIN CONFIGURATIONS (continued BOTTOM VIEW SIDE VIEW SFN (APPROX. 6.0mm x 6.0mm x 0.9mm) NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO- MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE INFORMATION, APPLICATION NOTE 4132: ATTACHMENT METHODS FOR ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DESCRIPTION from EC-table header to PUP from 0 ...