M45PE40-VMP6G NUMONYX, M45PE40-VMP6G Datasheet - Page 22
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M45PE40-VMP6G
Manufacturer Part Number
M45PE40-VMP6G
Description
IC FLASH 4MBIT 75MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M45PE40-VMP6G.pdf
(49 pages)
Specifications of M45PE40-VMP6G
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Clock Frequency
25MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
VDFPN
No. Of Pins
8
Base Number
45
Frequency
75MHz
Ic Generic Number
45PE40
Memory Configuration
512K X 8
Interface Type
Serial, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M45PE40-VMP6G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
M45PE40-VMP6G
Manufacturer:
MICRON
Quantity:
20 000
Instructions
6.5
22/49
Read data bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on serial data output (Q), each bit being shifted out, at a maximum
frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any read data bytes (READ)
instruction, while an erase, program or write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 10. Read data bytes (READ) instruction sequence and data-out sequence
1. Address bits A23 to A19 are don’t care.
S
C
D
Q
R
0
, during the falling edge of Serial Clock (C).
1
High Impedance
2
Instruction
3
4
5
6
7
MSB
23
8
22 21
Figure
9 10
24-bit address
10.
3
28 29 30 31 32 33 34 35
2
1
0
MSB
7
6
5
Data out 1
4
3
36 37 38
2
1
39
0
M45PE40
7
Data out 2
AI03748D