CY62137EV30LL-45ZSXI Cypress Semiconductor Corp, CY62137EV30LL-45ZSXI Datasheet - Page 6

• Manufacturer Part Number: CY62137EV30LL-45ZSXI
• Description: IC SRAM 2MBIT 45NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62137EV30LL-45ZSXI

• Memory Size: 2M (128K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 20 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2069; CY62137EV30LL-45ZSXI

Switching Characteristics
Over the Operating Range
Document #: 38-05443 Rev. *D
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Refer application note,
17. At any given temperature and voltage condition, t
18. t
19. The internal write time of the memory is defined by the overlap of WE, CE = V
levels of 0 to V
device.
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
HZOE
Parameter
, t
HZCE
[19]
, t
HZBE
CC(typ.)
[15, 16]
, and t
, and output loading of the specified I
HZWE
transitions are measured when the outputs enter a high impedance state.
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to LOW Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to power-up
CE HIGH to power-down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to HIGH Z
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High-Z
WE HIGH to Low-Z
HZCE
is less than t
[17]
Description
[17]
[17, 18]
[17, 18]
[17, 18]
[17]
OL
/I
OH
[17]
as shown in
LZCE
[17, 18]
, t
HZBE
IL
AC Test Loads and
is less than t
, BHE and BLE = V
LZBE
, t
HZOE
Waveforms.
IL
. All signals must be ACTIVE to initiate a write and any of these
is less than t
Min
45
10
10
45
35
35
35
35
25
10
–
–
–
5
–
–
0
–
–
5
–
0
0
0
–
LZOE
45 ns
CY62137EV30 MoBL
, and t
HZWE
Max
45
45
22
18
18
45
45
18
18
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AN13842
is less than t
for more information.
CC(typ)
LZWE
Page 6 of 15
/2, input pulse
for any given
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
[+] Feedback