CY62137EV30LL-45ZSXI Cypress Semiconductor Corp, CY62137EV30LL-45ZSXI Datasheet

IC SRAM 2MBIT 45NS 44TSOP

CY62137EV30LL-45ZSXI

Manufacturer Part Number
CY62137EV30LL-45ZSXI
Description
IC SRAM 2MBIT 45NS 44TSOP
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr
Datasheet

Specifications of CY62137EV30LL-45ZSXI

Memory Size
2M (128K x 16)
Package / Case
44-TSOP II
Format - Memory
RAM
Memory Type
SRAM
Speed
45ns
Interface
Parallel
Voltage - Supply
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Access Time
45 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.2 V
Maximum Operating Current
20 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
2.5 V, 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2069
CY62137EV30LL-45ZSXI
Cypress Semiconductor Corporation
Document #: 38-05443 Rev. *D
Features
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com.
Very high speed: 45 ns
Wide voltage range: 2.20 V to 3.60 V
Pin compatible with CY62137CV30
Ultra low standby power
Ultra low active power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Byte power-down feature
Offered in Pb-free 48-ball very fine ball grid array (VFBGA)
and 44-pin thin small outline package (TSOPII) package
Pow er
Circuit
Typical standby current: 1 A
Maximum standby current: 7 A
Typical active current: 2 mA at f = 1 MHz
-
Down
A
A
A
A
A
A
A
A
A
A
A
10
6
5
4
3
2
1
0
9
8
7
CE
BHE
BLE
COLUMN DECODER
198 Champion Court
DATA IN DRIVERS
RAM Array
128K x 16
Functional Description
The CY62137EV30
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption when deselected (CE HIGH or
both BLE and BHE are HIGH). The input and output pins (I/O
through I/O
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by asserting Chip
Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
I/O
(A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appears on I/O
LOW, then data from memory appears on I/O
the
and write modes.
The CY62137EV30 is available in 48-ball VFBGA and 44-pin
TSOPII packages.
2-Mbit (128K x 16) Static RAM
0
7
through A
Truth Table
), is written into the location specified on the address pins
15
San Jose
16
) are placed in a high impedance state when:
). If Byte High Enable (BHE) is LOW, then data
on page 10 for a complete description of read
8
[1]
through I/O
0
,
is a high performance CMOS static RAM
to I/O
CA 95134-1709
I/O
I/O
CY62137EV30 MoBL
0
8
– I/O
– I/O
7
. If Byte High Enable (BHE) is
BLE
BHE
WE
CE
OE
15
0
7
15
) is written into the location
through A
Revised January 17, 2011
16
).
8
to I/O
408-943-2600
0
through
15
. See
®
) in
0
®
[+] Feedback

Related parts for CY62137EV30LL-45ZSXI

CY62137EV30LL-45ZSXI Summary of contents

Page 1

... BHE Circuit BLE Note 1. For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05443 Rev. *D 2-Mbit (128K x 16) Static RAM Functional Description The CY62137EV30 organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ ...

Page 2

Contents Pin Configurations ............................................................ 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform................................................. 5 Switching Characteristics ................................................ ...

Page 3

Pin Configurations [2, 3] VFBGA (Top View BLE I/O BHE I/O I Vcc A ...

Page 4

Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ............................... –65 ° 150 °C Ambient temperature with power applied ......................................... –55 ° 125 ...

Page 5

Capacitance Parameter Description [10] C Input capacitance IN C Output capacitance OUT Thermal Resistance Parameter [10] Description  Thermal resistance JA (junction to ambient)  Thermal resistance JC (junction to case OUTPUT 30 pF INCLUDING JIG AND ...

Page 6

... HZOE HZCE HZBE HZWE 19. The internal write time of the memory is defined by the overlap of WE signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05443 Rev. *D Description ...

Page 7

Switching Waveforms Figure 2. Read Cycle 1: Address Transition Controlled ADDRESS DATA OUT PREVIOUS DATA VALID Figure 3. Read Cycle No Controlled ADDRESS CE t ACE OE BHE/BLE t LZOE t DBE t LZBE HIGH IMPEDANCE DATA OUT ...

Page 8

... NOTE 26 t HZOE Notes 23. The internal write time of the memory is defined by the overlap of WE these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write 24. Data I/O is high impedance ...

Page 9

Switching Waveforms (continued) Figure 6. Write Cycle No Controlled, OE LOW ADDRESS CE BHE/BLE NOTE 28 DATAI/O t HZWE Figure 7. Write Cycle No. 4: BHE/BLE Controlled, OE LOW ADDRESS CE BHE/BLE ...

Page 10

Truth Table BHE BLE [29 [29 ...

Page 11

... Ordering Information Speed Ordering Code (ns) 45 CY62137EV30LL-45BVXI 45 CY62137EV30LL-45ZSXI Ordering Code Definition CY 621 3 7E V30 LL Document #: 38-05443 Rev. *D Package Package Type Diagram 51-85150 48-Ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) 51-85087 44-Pin TSOP II (Pb-free) 45 XXX X Temperature Grades I = Industrial ...

Page 12

Package Diagrams Figure 8. 48-Pin VFBGA ( mm) (51-85150) Document #: 38-05443 Rev. *D ® CY62137EV30 MoBL 51-85150-*F Page [+] Feedback ...

Page 13

... Package Diagrams (continued) Acronyms Acronym Description CMOS complementary metal oxide semiconductor I/O input/output SRAM static random access memory VFBGA very fine ball gird array TSOP thin small outline package Document #: 38-05443 Rev. *D Figure 9. 44-Pin TSOP II (51-85087) Document Conventions Units of Measure Symbol ° ...

Page 14

Document History Page Document Title: CY62137EV30 MoBL Document Number: 38-05443 Orig. of Submission Rev. ECN No. Change ** 203720 AJU See ECN *A 234196 AJU See ECN *B 427817 NXR See ECN *C 2604685 VKN/PYRS *D 3143896 RAME 01/17/2011 Document ...

Page 15

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

Related keywords