CY62137EV30LL-45ZSXI Cypress Semiconductor Corp, CY62137EV30LL-45ZSXI Datasheet - Page 8

• Manufacturer Part Number: CY62137EV30LL-45ZSXI
• Description: IC SRAM 2MBIT 45NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62137EV30LL-45ZSXI

• Memory Size: 2M (128K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 20 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2069; CY62137EV30LL-45ZSXI

Switching Waveforms
Notes
Document #: 38-05443 Rev. *D
23. The internal write time of the memory is defined by the overlap of WE, CE = V
24. Data I/O is high impedance if OE = V
25. If CE goes HIGH simultaneously with WE = V
26. During this period, the I/Os are in output state and input signals should not be applied.
ADDRESS
these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write
DATA I/O
ADDRESS
DATA I/O
BHE/BLE
BHE/BLE
CE
WE
OE
OE
WE
CE
NOTE 26
NOTE
26
(continued)
IH
.
t
SA
t
t
HZOE
HZOE
Figure 4. Write Cycle No. 1: WE Controlled
Figure 5. Write Cycle No. 2: CE Controlled
IH
, the output remains in a high impedance state.
t
SA
t
AW
t
AW
t
SCE
t
WC
t
WC
IL
, BHE and BLE = V
t
t
BW
BW
DATA
DATA
t
t
PWE
t
t
SD
PWE
SD
t
IN
IN
SCE
IL
. All signals must be ACTIVE to initiate a write and any of
[23, 24, 25]
[23, 24, 25]
CY62137EV30 MoBL
t
HA
t
HA
t
t
HD
HD
Page 8 of 15
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