CY14E256L-SZ45XC Cypress Semiconductor Corp, CY14E256L-SZ45XC Datasheet - Page 11

IC NVSRAM 256KBIT 45NS 32SOIC

CY14E256L-SZ45XC

Manufacturer Part Number
CY14E256L-SZ45XC
Description
IC NVSRAM 256KBIT 45NS 32SOIC
Manufacturer
Cypress Semiconductor Corp
Type
NVSRAMr
Datasheet

Specifications of CY14E256L-SZ45XC

Format - Memory
RAM
Memory Type
NVSRAM (Non-Volatile SRAM)
Memory Size
256K (32K x 8)
Speed
45ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
32-SOIC (7.5mm Width)
Word Size
8b
Organization
32Kx8
Density
256Kb
Interface Type
Parallel
Access Time (max)
45ns
Operating Supply Voltage (typ)
5V
Package Type
SOIC
Operating Temperature Classification
Commercial
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temp Range
0C to 70C
Pin Count
32
Mounting
Surface Mount
Supply Current
70mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY14E256L-SZ45XC
Manufacturer:
CYPRESS
Quantity:
1 167
Part Number:
CY14E256L-SZ45XCT
Manufacturer:
CYPRESS
Quantity:
3 020
Switching Waveforms
Notes
Document Number: 001-06968 Rev. *H
SRAM Write Cycle
t
t
t
t
t
t
t
t
t
t
12. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
13. HSB must be high during SRAM WRITE cycles.
14. CE or WE must be greater than V
WC
PWE
SCE
SD
HD
AW
SA
HA
HZWE
LZWE
Parameter
Cypress
[11]
[11,12]
ADDRESS
DATA OUT
DATA IN
Parameter
CE
WE
ADDRESS
DATA OUT
DATA IN
t
t
t
t
t
t
t
t
t
t
AVAV
WLWH,
ELWH,
DVWH,
WHDX,
AVWH,
AVWL,
WHAX,
WLQZ
WHQX
WE
CE
t
t
t
t
t
t
t
ELEH
AVEL
AVEH
EHAX
WLEH
DVEH
EHDX
Alt
IH
during address transitions.
PREVIOUS DATA
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
Figure 10. SRAM Write Cycle 2: CE Controlled
Figure 9. SRAM Write Cycle 1: WE Controlled
t
t
SA
SA
Description
t
AW
t
HZWE
HIGH IMPEDANCE
t
t
AW
t
PWE
SCE
t
WC
t
t
SCE
WC
t
HIGH IMPEDANCE
PWE
DATA VALID
t
SD
Min
t
20
25
20
10
20
SD
0
0
0
5
DATA VALID
25 ns
Max
10
[13, 14]
[13, 14]
t
t
HD
HA
t
HA
Min
t
35
25
25
12
25
HD
0
0
0
5
35 ns
t
LZWE
Max
13
Min
45
30
30
15
30
0
0
0
5
CY14E256L
45 ns
Page 11 of 19
Max
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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