CY14E256L-SZ45XC Cypress Semiconductor Corp, CY14E256L-SZ45XC Datasheet - Page 6

• Manufacturer Part Number: CY14E256L-SZ45XC
• Description: IC NVSRAM 256KBIT 45NS 32SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14E256L-SZ45XC

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-SOIC (7.5mm Width)
• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 70mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Protection
The CY14E256L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
mode (both CE and WE are low) at power up after a RECALL or
after a STORE, the WRITE is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brown out conditions.
Noise Considerations
The CY14E256L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Hardware Protect
The CY14E256L offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage condi-
tions. When V
operations and SRAM WRITEs are inhibited. AutoStore can be
completely disabled by tying VCC to ground and applying + 5V
to V
STOREs are only initiated by explicit request using either the
software sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the CY14E256L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14E256L depends on the
following items:
■
■
■
■
■
■
■
Document Number: 001-06968 Rev. *H
The duty cycle of chip enable
The overall cycle rate for accesses
The ratio of READs to WRITEs
CMOS versus TTL input levels
The operating temperature
The V
I/O loading
CAP
CC
. This is the AutoStore Inhibit mode; in this mode,
CC
is less than V
CC
level
Figure 4
and V
CAP
<V
SS,
shows the relationship between I
SWITCH
using leads and traces that are as short
SWITCH
, all externally initiated STORE
. If the CY14E256L is in a WRITE
CC
and
Figure 4. Current Versus Cycle Time (READ)
Figure 5. Current Versus Cycle Time (WRITE)
Preventing Store
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a V
because it has to overpower the internal pull down device. This
device drives HSB LOW for 20 μs at the onset of a STORE.
When the CY14E256L is connected for AutoStore operation
(system V
and V
attempts to pull HSB LOW. If HSB does not actually get below
V
attempt.
IL
, the part stops trying to pull HSB LOW and abort the STORE
CC
crosses V
CC
connected to V
SWITCH
on the way down, the CY14E256L
CC
and a 68 μF capacitor on V
OH
CY14E256L
of at least 2.2V,
Page 6 of 19
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