CY7C144AV-25AXC Cypress Semiconductor Corp, CY7C144AV-25AXC Datasheet - Page 6

• Manufacturer Part Number: CY7C144AV-25AXC
• Description: IC SRAM 64KBIT 25NS 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C144AV-25AXC

• Memory Size: 64K (8K x 8)
• Package / Case: 64-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 25 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 165 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 8K X 8
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2156; CY7C144AV-25AXC

prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it. If an
application does not require message passing, do not connect
the interrupt pin to the processor’s interrupt request input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both
ports’ CEs are asserted and an address match occurs within
t
access. If t
permission to the location, but it is not predictable which port
will get that permission. BUSY will be asserted t
address match or t
Master/Slave
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (t
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Semaphore Operation
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV provide eight semaphore latches, which
are
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates
that a resource is in use. For example, if the left port wants to
Document #: 38-06051 Rev. *C
PS
of each other, the busy logic will determine which port has
separate
PS
is violated, one port will definitely gain
from
BLC
after CE is taken LOW.
the
dual-port
memory
BLC
BLA
locations.
or t
after an
BLA
),
request a given resource, it sets a latch by writing a zero to a
semaphore location. The left port then verifies its success in
setting the latch by reading it. After writing to the semaphore,
SEM or OE must be deasserted for t
read the semaphore. The semaphore value will be available
t
the left port was successful (reads a zero), it assumes control
of the shared resource, otherwise (reads a one) it assumes the
right port has control and continues to poll the semaphore.
When the right side has relinquished control of the semaphore
(by writing a one), the left side will succeed in gaining control
of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.
When reading a semaphore, all data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within t
definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore.
SWRD
+ t
DOE
after the rising edge of the semaphore write. If
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
SPS
of each other, the semaphore will
CY7C007AV/017AV
SOP
0
before attempting to
is used. If a zero is
0–2
represents the
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