IDT70V9269S12PRFI IDT, Integrated Device Technology Inc, IDT70V9269S12PRFI Datasheet - Page 3

IC SRAM 256KBIT 12NS 128TQFP

IDT70V9269S12PRFI

Manufacturer Part Number
IDT70V9269S12PRFI
Description
IC SRAM 256KBIT 12NS 128TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT70V9269S12PRFI

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
256K (16K x 16)
Speed
12ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
70V9269S12PRFI
800-1399

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70V9269S12PRFI
Manufacturer:
IDT
Quantity:
881
Part Number:
IDT70V9269S12PRFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Truth Table I—Read/Write and Enable Control
NOTES:
1. "H" = V
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4 LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE
Pin Names
R/W
I/O
CLK
CE
OE
A
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
0L
OE
X
X
X
X
X
X
0L
L
L
L
L
H
0L,
L
L
L
L
- A
L
Left Port
- I/O
CE
14L
L
L
IH,
L
1L
15L
CLK
(1)
"L" = V
1
are single buffered when FT/PIPE = V
IL,
CE
V
V
DD
SS
"X" = Don't Care.
H
X
L
L
L
L
L
L
L
L
0
R/W
I/O
CLK
CE
OE
A
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
(5)
0R
0R
R
0R,
R
R
R
R
Right Port
- A
R
- I/O
CE
CE
14R
R
X
H
H
H
H
H
H
H
H
R
L
R
1
1R
(5)
15R
(1)
UB
X
X
H
H
H
L
L
L
L
L
(4)
Chip Enables
Read/Write Enable
Output Enable
Data Input/Output
Clock
Upper Byte Select
Lower Byte Select
Counter Enable
Counter Reset
Flow-Through / Pipeline
Power (3.3V)
Ground (0V)
Address
Address Strobe Enable
LB
X
X
H
H
L
L
H
L
L
L
(4)
IL
. CEo and CE
Names
R/W
(3)
X
X
X
X
L
L
L
H
H
H
(2)
(2)
Upper Byte
3743 tbl 01
DATA
DATA
1
DATA
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
I/O
are double buffered when FT/PIPE = V
D
8-15
IN
OUT
OUT
IN
6.42
3
NOTES:
1. Address A
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CE
CE
i.e. the signals take two cycles to deselect.
0
0
Lower Byte
DATA
DATA
and CE
and CE
DATA
DATA
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
I/O
0-7
OUT
OUT
14
IN
IN
X
1
1
Industrial and Commercial Temperature Ranges
are double buffered when FT/PIPE = V
is a NC for IDT70V9269.
are single buffered when FT/PIPE = V
(1,2,3)
Deselected–Power Down
Deselected–Power Down
Both Bytes Deselected
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
IH
, i.e. the signals take two cycles to deselect.
MODE
IL
IH
,
,
3743 tbl 02

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