MT47H32M8BP-37E:B TR Micron Technology Inc, MT47H32M8BP-37E:B TR Datasheet - Page 12

• Manufacturer Part Number: MT47H32M8BP-37E:B TR
• Description: IC DDR2 SDRAM 256MBIT 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M8BP-37E:B TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 3.75ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 500ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 160mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1049-2

Figure 4: 32 Meg x 8 Functional Block Diagram
Figure 5: 16 Meg x 16 Functional Block Diagram
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
BA0–BA1
BA0–BA1
A0–A12,
A0–A12,
RAS#
CAS#
WE#
RAS#
CAS#
ODT
CKE
CK#
ODT
WE#
CS#
CKE
CK#
CK
CS#
CK
15
15
Address
register
Address
register
registers
registers
Mode
Mode
Control
Control
logic
logic
15
15
counter
Refresh
Refresh
counter
13
13
9
10
2
2
13
13 Row-
address
address
2
2
MUX
Row-
MUX
control
Column-
counter/
address
Bank
logic
Column-
counter/
address
latch
control
13
Bank
logic
latch
13
latch and
decoder
address
Bank 0
latch and
decoder
row-
address
Bank 0
Bank 1
row-
Bank 1
Bank 2
Bank 2
Bank 3
Bank 3
8
2
7
2
8,192
8,192
DM mask logic
DM mask logic
Sense amplifiers
I/O gating
(8,192 x 256 x 32)
(8,192 x 128 x 64)
Sense amplifiers
I/O gating
Column
decoder
decoder
Column
Memory
8,192
Memory
8,192
Bank 0
Bank 0
(x32)
256
array
array
Bank 1
(x64)
Bank 1
128
Bank 2
Bank 2
Bank 3
Bank 3
Column 0, Column 1
Column 0, Column 1
Internal
CK, CK#
Internal
CK, CK#
32
12
64
32
32
64
READ
latch
64
CK out
drivers
WRITE
FIFO
READ
latch
CK out
and
CK in
drivers
WRITE
Column 0, Column 1
CK in
FIFO
and
Column 0, Column 1
8
8
8
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Mask
Data
16
16
16
16
MUX
32
Mask
Data
4
generator
64
8
MUX
8
8
DQS
1
1
1
1
8
8
256Mb: x4, x8, x16 DDR2 SDRAM
registers
generator
Input
Data
2
2
2
2
16
16
16
16
DQS
registers
8
Input
Data
8
8
1
1
1
1
8
8
DQS, DQS#
16
16
16
16
16
2
2
2
2
UDQS, UDQS#
LDQS, LDQS#
1
8
2
CK, CK#
DRVRS
Functional Block Diagrams
CK, CK#
16
4
DLL
RCVRS
DRVRS
2
2
DLL
4
RCVRS
sw1 sw2
sw1 sw2
sw1 sw2
sw1 sw2
R1
R1
R1
R1
R1
R1
sw1 sw2
sw1 sw2
sw1 sw2
sw1 sw2
R1
R1
R1
R1
R1
R1
ODT control
ODT control
©2003 Micron Technology, Inc. All rights reserved.
R2
R2
R2
R2
R2
R2
VssQ
R2
R2
R2
R2
R2
R2
VssQ
sw3
sw3
sw3
sw3
sw3
sw3
sw3
sw3
R3
R3
R3
R3
R3
R3
R3
R3
R3
R3
R3
R3
V
V
dd
dd
Q
Q
DQ0–DQ15
UDQS, UDQS#
LDQS, LDQS#
UDM, LDM
RDQS
DM
DQ0–DQ7
RDQS#
DQS, DQS#