ZLF645S2864GP0001T Maxim Integrated, ZLF645S2864GP0001T Datasheet - Page 180

• Manufacturer Part Number: ZLF645S2864GP0001T
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645S2864GP0001T

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 2 V to 3.6 V
• Interface Type: UART
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• Processor Series: ZLF645
• Program Memory Type: Flash

19-4572; Rev 0; 4/09
Table 83. User Option Byte 0 (OPT0)
Bit Position
[7]
[6:0]
Bit
Field
Erased State
Flash Address
User Option Bit Locations in Flash Memory
User Option Bit Shadow Register Access
User Option Byte 0 and Option Byte 0 Shadow 
Register Definitions
The Option Bit Shadow registers are part of the ZLF645’s Register File and are accessible
for read/write access.
The user option bits are located in the upper two bytes of the Information block, address
FFh and FEh.
Except for bits 0 and 1 of the User Option Byte 1 Shadow register, the CPU has full 
read/write access to all the User Option Byte Shadow registers at the address locations
given in register tables for each register.
This option byte allows user control over the enabling of the ZLF645’s I/O pull-ups and
the conditions under which the devices watchdog timer is enabled. For its associated
shadow registers, until the registers are loaded with their corresponding option bit values,
their outputs will be in an unknown state.
Value
1
0
WDT
7
1
Description
WDT—Watchdog Timer Enable
WDT = 1: WDT is enabled by WDT instruction only. 
WDT = 0: WDT is always enabled.
P4PU through P0LPU—GPIO Pin Pull-Up Enables
P4PU = 1: Port 4 Pull-ups disabled. 
P4PU = 0: Port 4 Pull-ups enabled.
P3PU = 1: Port 3 Pull-ups disabled. 
P3PU = 0: Port 3 Pull-ups enabled.
P4PU
6
1
Flash Memory Information Area address: FEH
P3PU
5
1
P2PU
4
1
P1HPU
3
1
ZLF645 Series Flash MCUs
P1LPU
2
1
Product Specification
P0HPU
1
1
Operation
P0LPU
0
1
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