AT25DF021-MH-T Atmel, AT25DF021-MH-T Datasheet - Page 10

• Manufacturer Part Number: AT25DF021-MH-T
• Description: IC FLASH 2MBIT 70MHZ 8UDFN
• Manufacturer: Atmel

Specifications of AT25DF021-MH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 2M (256K x 8)
• Speed: 70MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-1.
Figure 8-2.
8.2
10
SCK
SO
CS
Block Erase
SI
AT25DF021
Byte Program
Page Program
SCK
SO
CS
SI
HIGH-IMPEDANCE
MSB
0
0
0
1
A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single oper-
ation by using one of three different opcodes for the Block Erase command. An opcode of 20h is
used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h
is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable
command must have been previously issued to the device to set the WEL bit of the Status Reg-
ister to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h,
52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the three
address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be
clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deas-
serted, the device will erase the appropriate block. The erasing of the block is internally self-
timed and should take place in a time of t
Since the Block Erase command erases a region of bytes, the lower order address bits do not
need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be
ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase,
address bits A14-A0 will be ignored, and for a 64-Kbyte erase, address bits A15-A0 will be
ignored by the device. Despite the lower order address bits not being decoded by the device, the
complete three address bytes must still be clocked into the device before the CS pin is deas-
serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation and no erase operation will be performed.
0
2
OPCODE
0
HIGH-IMPEDANCE
MSB
3
0
0
0
4
0
1
0
5
0
2
OPCODE
1
6
0
3
0
7
0
MSB
4
A
ADDRESS BITS A23-A0
8
0
5
A
9
1
6
A
0
7
MSB
A
8
A
A
29 30
9
ADDRESS BITS A23-A0
A
A
10 11
A
A
31 32
MSB
A
D
12
A
D
33
DATA IN BYTE 1
D
34
BLKE
D
35
A
29 30
.
D
36
A
D
37 38
A
31 32
D
MSB
D
D
39
D
33
D
34
DATA IN
D
35
MSB
D
D
36
D
DATA IN BYTE n
D
37 38
D
D
D
D
39
D
D
D
D
3677D–DFLASH–04/09