AT26DF081A-SU Atmel, AT26DF081A-SU Datasheet - Page 23

• Manufacturer Part Number: AT26DF081A-SU
• Description: IC FLASH 8MBIT 70MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT26DF081A-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 8M (4096 pages x 256 bytes)
• Speed: 70MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT26DF081-SU; AT26DF081-SU

10. Status Register Commands
10.1
Table 10-1.
Notes:
3600G–DFLASH–06/09
Bit
3:2
7
6
5
4
1
0
(1)
Read Status Register
1. Only bit 7 of the Status Register will be modified when using the Write Status Register command.
2. R/W = Readable and writable
RDY/BSY
SPRL
WPP
SWP
SPM
WEL
EPE
R = Readable only
Status Register Format
Sector Protection Registers Locked
Sequential Program Mode Status
Erase/Program Error
Write Protect (WP) Pin Status
Software Protection Status
Write Enable Latch Status
Ready/Busy Status
The Status Register can be read to determine the device's ready/busy status, as well as the sta-
tus of many other functions such as Hardware Locking and Software Protection. The Status
Register can be read at any time, including during an internally self-timed program or erase
operation.
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be
clocked into the device. After the last bit of the opcode has been clocked in, the device will begin
outputting Status Register data on the SO pin during every subsequent clock cycle. After the last
bit (bit 0) of the Status Register has been clocked out, the sequence will repeat itself starting
again with bit 7 as long as the CS pin remains asserted and the SCK pin is being pulsed. The
data in the Status Register is constantly being updated, so each repeating sequence will output
new data.
Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin
into a high-impedance state. The CS pin can be deasserted at any time and does not require
that a full byte of data be read.
Name
Type
R/W
R
R
R
R
R
R
(2)
Description
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
Sector Protection Registers are unlocked (default).
Sector Protection Registers are locked.
Byte/Page Programming Mode (default).
Sequential Programming Mode entered.
Erase or program operation was successful.
Erase or program error detected.
WP is asserted.
WP is deasserted.
All sectors are software unprotected (all Sector
Protection Registers are 0).
Some sectors are software protected. Read individual
Sector Protection Registers to determine which
sectors are protected.
Reserved for future use.
All sectors are software protected (all Sector
Protection Registers are 1 – default).
Device is not write enabled (default).
Device is write enabled.
Device is ready.
Device is busy with an internal operation.
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