MA240026 Microchip Technology, MA240026 Datasheet - Page 53

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MA240026

Manufacturer Part Number
MA240026
Description
Daughter Cards & OEM Boards PIC24FJ16MC102 Plug-In Module
Manufacturer
Microchip Technology
Datasheet

Specifications of MA240026

Rohs
yes
Data Bus Width
16 bit
Description/function
PIC24F 28 Pin QFN to 100 Pin Plug-in-Module
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MA240026
Manufacturer:
MICROCHIP
Quantity:
12 000
REGISTER 5-1:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
Note 1:
R/SO-0
WR
U-0
2:
(1)
These bits can only be reset on POR.
All other combinations of NVMOP<3:0> are unimplemented.
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
0 = The program or erase operation completed normally
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command
0 = Perform the program operation specified by NVMOP<3:0> on the next WR command
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits
If ERASE = 1:
1111 = No operation
1101 = Erase General Segment
1100 = No operation
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = No operation
If ERASE = 0:
1111 = No operation
1101 = No operation
1100 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = No operation
0000 = No operation
R/W-0
R/W-0
ERASE
WREN
cleared by hardware once operation is complete
automatically on any set attempt of the WR bit)
NVMCON: FLASH MEMORY CONTROL REGISTER
(1)
(1)
SO = Settable only bit
W = Writable bit
‘1’ = Bit is set
R/W-0
WRERR
U-0
(1)
U-0
U-0
Preliminary
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
(1)
PIC24FJ16MC101/102
R/W-0
U-0
NVMOP<3:0>
(1)
x = Bit is unknown
R/W-0
U-0
(2)
(1)
DS39997B-page 53
R/W-0
U-0
(1)
bit 8
bit 0

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