MA240026 Microchip Technology, MA240026 Datasheet - Page 60

• Manufacturer Part Number: MA240026
• Description: Daughter Cards & OEM Boards PIC24FJ16MC102 Plug-In Module
• Manufacturer: Microchip Technology

Specifications of MA240026

• Rohs: yes
• Data Bus Width: 16 bit
• Description/function: PIC24F 28 Pin QFN to 100 Pin Plug-in-Module
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V

PIC24FJ16MC101/102
6.4
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to
minimum pulse width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
register (RCON) is set to indicate the MCLR Reset.
6.4.1
Many systems have external supervisory circuits that
generate Reset signals to Reset multiple devices in the
system. This external Reset signal can be directly con-
nected to the MCLR pin to Reset the device when the
rest of system is Reset.
6.4.2
When using the internal power supervisory circuit to
Reset the device, the external Reset pin (MCLR)
should be tied directly or resistively to V
the MCLR pin will not be used to generate a Reset. The
external Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.5
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a spe-
cial Reset state. This Reset state will not re-initialize the
clock. The clock source in effect prior to the RESET
instruction will remain. SYSRST is released at the next
instruction cycle, and the Reset vector fetch will
commence.
The Software Reset (Instruction) Flag bit (SWR) in the
Reset Control register (RCON<6>) is set to indicate the
software Reset.
DS39997B-page 60
Section 26.0 “Electrical Characteristics”
External Reset (EXTR)
Software RESET Instruction (SWR)
EXTERNAL SUPERVISORY
CIRCUIT
INTERNAL SUPERVISORY CIRCUIT
DD
. In this case,
Preliminary
for
6.6
Whenever a Watchdog Time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag bit (WDTO) in the
Reset Control register (RCON<4>) is set to indicate the
Watchdog Reset. Refer to
Timer (WDT)”
Reset.
6.7
If a lower-priority hard trap occurs while a higher-prior-
ity trap is being processed, a hard trap conflict Reset
occurs. The hard traps include exceptions of priority
level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into
this category.
The Trap Reset Flag bit (TRAPR) in the Reset Control
register (RCON<15>) is set to indicate the Trap Conflict
Reset. Refer to
more information on trap conflict Resets.
6.8
To maintain the integrity of the peripheral pin select
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell dis-
turbances caused by ESD or other external events), a
configuration mismatch Reset occurs.
The Configuration Mismatch Flag bit (CM) in the Reset
Control register (RCON<9>) is set to indicate the con-
figuration mismatch Reset. Refer to
Ports”
mismatch Reset.
Note:
for more information on the configuration
Watchdog Time-out Reset (WDTO)
Trap Conflict Reset
Configuration Mismatch Reset
The configuration mismatch feature and
associated Reset flag is not available on
all devices.
Section 7.0 “Interrupt Controller”
for more information on Watchdog
© 2011 Microchip Technology Inc.
Section 23.4 “Watchdog
Section 10.0 “I/O
for