IS61LV256AL-10JLI-TR ISSI, Integrated Silicon Solution Inc, IS61LV256AL-10JLI-TR Datasheet - Page 8

• Manufacturer Part Number: IS61LV256AL-10JLI-TR
• Description: IC SRAM 256KBIT 10NS 28SOJ
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LV256AL-10JLI-TR

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 256K (32K x 8)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOJ
• Density: 256Kb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 15b
• Package Type: SOJ
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 25mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Word Size: 8b
• Number Of Words: 32K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61LV256AL
WRITE CYCLE NO. 3
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE > V
8
WRITE CYCLE NO. 2
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
ADDRESS
D
D
OUT
OUT
WE
D
WE
OE
D
CE
OE
CE
IN
IN
LOW
LOW
LOW
t
SA
t
DATA UNDEFINED
(WE Controlled, OE is LOW During Write Cycle)
(WE Controlled, OE is HIGH During Write Cycle)
DATA UNDEFINED
SA
Ih
.
VALID ADDRESS
t
t
t
t
AW
AW
HZWE
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
WC
HIGH-Z
Integrated Silicon Solution, Inc. — 1-800-379-4774
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
(1)
(1,2)
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
CE_WR2.eps
CE_WR3.eps
07/29/09
Rev. C