IS61C256AL-12TLI ISSI, Integrated Silicon Solution Inc, IS61C256AL-12TLI Datasheet - Page 7

IC SRAM 256KBIT 12NS 28TSOP

IS61C256AL-12TLI

Manufacturer Part Number
IS61C256AL-12TLI
Description
IC SRAM 256KBIT 12NS 28TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
Asynchronousr
Datasheet

Specifications of IS61C256AL-12TLI

Memory Size
256K (32K x 8)
Package / Case
28-TSOP
Interface
Parallel
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Speed
12ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Access Time
12 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Current
25 mA
Organization
32 K x 8
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
5 V
Density
256Kb
Access Time (max)
12ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
15b
Package Type
TSOP-I
Operating Temp Range
-40C to 85C
Supply Current
25mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Word Size
8b
Number Of Words
32K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1031

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61C256AL-12TLI
Manufacturer:
ISSI
Quantity:
6 447
Part Number:
IS61C256AL-12TLI
Manufacturer:
ISSI
Quantity:
135
Part Number:
IS61C256AL-12TLI
Manufacturer:
ISSI
Quantity:
1 301
Part Number:
IS61C256AL-12TLI
Manufacturer:
ISSI
Quantity:
20 000
IS61C256AL
WRITE CYCLE NO. 2
WRITE CYCLE NO. 3
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. B
10/23/06
ADDRESS
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
D
D
OUT
WE
D
OE
CE
OUT
WE
D
OE
CE
IN
IN
LOW
LOW
LOW
t
SA
t
DATA UNDEFINED
SA
DATA UNDEFINED
(OE is HIGH During Write Cycle)
(OE is LOW During Write Cycle)
V
IH
.
VALID ADDRESS
t
t
t
t
AW
HZWE
AW
HZWE
VALID ADDRESS
t
t
1-800-379-4774
PWE1
WC
t
t
PWE2
(1)
WC
(1,2)
HIGH-Z
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
ISSI
CE_WR2.eps
CE_WR3.eps
®
7

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