ADP1046ADC1-EVALZ Analog Devices, ADP1046ADC1-EVALZ Datasheet - Page 32

• Manufacturer Part Number: ADP1046ADC1-EVALZ
• Description: Power Management IC Development Tools
• Manufacturer: Analog Devices
• Type: Power Switchesr
• Series: ADP1046Ar

Specifications of ADP1046ADC1-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP1046A
• Input Voltage: 36 V to 60 V
• Output Voltage: 2.5 V
• Description/function: Daughter card for ADP1046A
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: ADP1046A

ADP1046A
VOLT-SECOND BALANCE
The
balance in the main transformer when operating in full-bridge
topology. This circuit eliminates the need for a dc blocking capac-
itor. In interleaved topologies, volt-second balance can also be
used for current balancing to ensure that each interleaved phase
contributes equal power.
The circuit monitors the current flowing in both legs of the full-
bridge topology and stores this information. It compensates the
selected PWM signals to ensure equal current flow in both legs
of the full-bridge topology. The input is through the CS1 pin.
Several switching cycles are required for the circuit to operate
effectively. The maximum amount of modulation applied to
each edge of the selected PWM outputs is programmable to
±80 ns or ±160 ns in Register 0x28[2].
The volt-second balance settings are programmed in Register 0x28
and in Register 0x76 through Register 0x78. It is recommended
that the Analog Devices software GUI be used to program these
settings.
The compensation of the PWM drive signals is performed on
the edges of two selected outputs. The SR1 and SR2 edges can
also be independently set to modulate due to the volt-second
balance circuit to maintain the timing relation to the primary
side signals.
DIGITAL LOAD LINE AND SLEW RATE
The
the power supply. This option is programmed in the load line
impedance register (Register 0x36). Two parameters can be
configured independently: slew rate and load line value.
The slew rate (Register 0x36[6:4]) determines how quickly the
output voltage is adjusted in response to a change in the digital
reference. Eight different settings are available.
The load line value (Register 0x36[2:0]) controls the slope of
the load line. The amount of output resistance introduced can
be calculated as follows:
where:
V
CS2 R
CS2 Range is 120 mV or 60 mV.
LOAD_SET[2:0] is the value of Bits[2:0] in Register 0x36
(0 to 7 decimal).
OUT_NOM
ADP1046A
ADP1046A
R
SENSE
OUT
is the nominal output voltage when VS3 = 1 V.
= 0.1 × V
is the sense resistor value.
has a dedicated circuit to maintain volt-second
can optionally introduce a digital load line into
OUT_NOM
× CS2 R
SENSE
/(CS2 Range × 2
LOAD_SET[2:0]
Rev. 0 | Page 32 of 88
)
For example, if V
CS2 Range = 120 mV, and LOAD_SET[2:0] = 3,
This feature can be used for advanced current sharing techniques.
By default, the load line is disabled. The load line is introduced
digitally by modifying the value of the digital reference based
on the CS2 reading.
Figure 43 and Figure 44 show the load line as a percentage of
V
OUT
R
vs. the R
100
OUT
100
99
98
97
96
95
94
93
92
91
90
98
96
94
92
90
88
0
0
= 0.1 × 12 V × 10 mΩ/(120 mV × 2
Figure 43. Load Line Settings with 120 mV CS2 Range
Figure 44. Load Line Settings with 60 mV CS2 Range
10
5
SENSE
SETTING 7
SETTING 6
SETTING 5
SETTING 4
SETTING 3
SETTING 2
SETTING 1
SETTING 0
SETTING 7
SETTING 6
SETTING 5
SETTING 4
SETTING 3
SETTING 2
SETTING 1
SETTING 0
20
10
OUT_NOM
voltage drop.
30
15
R
R
SENSE
SENSE
40
20
= 12 V, CS2 R
VOLTAGE DROP (mV)
VOLTAGE DROP (mV)
50
25
60
30
70
35
SENSE
80
40
= 10 mΩ,
90
45
3
) = 12.5 mΩ
Data Sheet
100
50
110
55
120
60