ADP1046ADC1-EVALZ Analog Devices, ADP1046ADC1-EVALZ Datasheet - Page 84

• Manufacturer Part Number: ADP1046ADC1-EVALZ
• Description: Power Management IC Development Tools
• Manufacturer: Analog Devices
• Type: Power Switchesr
• Series: ADP1046Ar

Specifications of ADP1046ADC1-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP1046A
• Input Voltage: 36 V to 60 V
• Output Voltage: 2.5 V
• Description/function: Daughter card for ADP1046A
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: ADP1046A

ADP1046A
RESONANT MODE REGISTER DESCRIPTIONS
Table 145. Register 0x40—PWM Switching Frequency Setting in Resonant Mode
Bits
[7:6]
[5:0]
Table 146. Register 0x41—OUTA Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 147. Register 0x42—Lowest Switching Frequency Limit Setting (Maximum Switching Cycle in Resonant Mode)
Bits
[7:0]
Table 148. Register 0x43—OUTA Falling Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 149. Register 0x44—Lowest Switching Frequency Limit Setting (Maximum Switching Cycle in Resonant Mode)
Bits
[7:4]
[3:0]
Bit Name
Reserved
Switching frequency
Bit Name
Δt
time of OUTA)
Bit Name
Lowest frequency
Bit Name
Δt
time of OUTA)
Bit Name
Lowest frequency
Reserved
1
2
(rising edge dead
(falling edge dead
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved.
This register sets the switching frequency of the PWM pins and enables resonant mode. To
enable resonant mode, set these bits to 0x3F (111111).
Description
This register sets Δt
switching cycle, t
Bit 7
0
0
…
1
Description
This register contains the eight MSBs of the 12-bit value of the lowest switching frequency (maxi-
mum switching cycle) limit. This value is always used with the top four bits of Register 0x44,
which contain the four LSBs of the lowest switching frequency limit. Each LSB of the 12-bit
value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x42
is set to 0xA0 (160 decimal) and Bits[7:4] of Register 0x44 are set to 0xF (15 decimal), the
maximum switching cycle is (160 × 16 + 15) × 5 ns = 12.875 μs, and the lowest switching
frequency limit is 1/12.875 μs = 77.7 kHz.
Description
This register sets Δt
point of the switching cycle, t
value is from 0x00 to 0x7F, the falling edge of OUTA is trailing t
to 0xFF, the falling edge of OUTA is leading t
Bit 7
0
0
…
0
1
…
1
Description
This register contains the four LSBs of the 12-bit value of the lowest switching frequency (maxi-
mum switching cycle) limit. This value is always used with the eight bits of Register 0x42, which
contain the eight MSBs of the lowest switching frequency limit. Each LSB of the 12-bit value
corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x42 is set
to 0xA0 (160 decimal) and Bits[7:4] of Register 0x44 are set to 0xF (15 decimal), the maximum
switching cycle is (160 × 16 + 15) × 5 ns = 12.875 μs, and the lowest switching frequency limit
is 1/12.875 μs = 77.7 kHz.
Reserved.
Bit 6
0
0
…
1
Bit 6
0
0
…
1
0
…
1
Rev. 0 | Page 84 of 88
A
. Each LSB corresponds to 5 ns of resolution.
1
2
Bit 5
0
0
…
1
Bit 5
0
0
…
1
0
…
1
, which is the delay of the rising edge of OUTA from the start of the
, which is the difference between the falling edge of OUTA and the mid-
B
Bit 4
0
0
…
1
Bit 4
0
0
…
1
0
…
1
. Each LSB corresponds to 5 ns of resolution. When the register
Bit 3
0
0
…
1
Bit 3
0
0
…
1
0
…
1
B
.
Bit 2
0
0
…
1
Bit 2
0
0
…
1
0
…
1
Bit 1
0
0
…
1
Bit 1
0
0
…
1
0
…
1
B
. When the value is from 0x80
Bit 0
0
1
…
1
Bit 0
0
1
…
1
0
…
1
Data Sheet
Δt
0 ns
5 ns trailing
…
635 ns trailing
640 ns leading
…
5 ns leading
Δt
0
5
…
1275
2
1
(ns)