ADP1046ADC1-EVALZ Analog Devices, ADP1046ADC1-EVALZ Datasheet - Page 86

• Manufacturer Part Number: ADP1046ADC1-EVALZ
• Description: Power Management IC Development Tools
• Manufacturer: Analog Devices
• Type: Power Switchesr
• Series: ADP1046Ar

Specifications of ADP1046ADC1-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP1046A
• Input Voltage: 36 V to 60 V
• Output Voltage: 2.5 V
• Description/function: Daughter card for ADP1046A
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: ADP1046A

ADP1046A
Table 154. Register 0x49—OUTC Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 155. Register 0x4A—Burst Mode Operation in Resonant Mode
Bits
[7:6]
[5:0]
Table 156. Register 0x4B—OUTC Falling Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 157. Register 0x4D—OUTD Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Bit Name
Δt
time of OUTC)
Bit Name
Burst mode enable
Burst mode offset
Bit Name
Δt
time of OUTC)
Bit Name
Δt
time of OUTD)
5
6
7
(rising edge dead
(falling edge dead
(rising edge dead
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This register sets Δt
point of the switching cycle, t
value is from 0x00 to 0x7F, the rising edge of OUTC is trailing t
to 0xFF, the rising edge of OUTC is leading t
Bit 7
0
0
…
0
1
…
1
Description
These bits are used to enable or disable burst mode operation.
Bit 7
0
0
1
1
These bits, along with the highest switching frequency limit, determine the threshold value for
enabling burst mode operation. For information about how to set this value, see the Light Load
Operation (Burst Mode) section. During burst mode, the PWM frequency is the maximum
frequency limit set in Register 0x46.
Description
This register sets Δt
switching cycle, t
Bit 7
0
0
…
1
Description
This register sets Δt
point of the switching cycle, t
value is from 0x00 to 0x7F, the rising edge of OUTD is trailing t
to 0xFF, the rising edge of OUTD is leading t
Bit 7
0
0
…
0
1
…
1
Bit 6
0
0
…
1
0
…
1
Bit 6
0
0
…
1
Bit 6
0
0
…
1
0
…
1
Bit 6
0
1
0
1
Rev. 0 | Page 86 of 88
C
. Each LSB corresponds to 5 ns of resolution.
5
6
7
Bit 5
0
0
…
1
0
…
1
Bit 5
0
0
…
1
Bit 5
0
0
…
1
0
…
1
, which is the difference between the rising edge of OUTC and the mid-
, which is the leading time of the falling edge of OUTC from the end of the
, which is the difference between the rising edge of OUTD and the mid-
B
Bit 4
0
0
…
1
0
…
1
Burst Mode
Disabled
Enabled for normal operation, but disabled during soft start
Disabled
Enabled for normal operation and during soft start
Bit 4
0
0
…
1
B
Bit 4
0
0
…
1
0
…
1
. Each LSB corresponds to 5 ns of resolution. When the register
. Each LSB corresponds to 5 ns of resolution. When the register
Bit 3
0
0
…
1
0
…
1
Bit 3
0
0
…
1
Bit 3
0
0
…
1
0
…
1
B
B
.
.
Bit 2
0
0
…
1
0
…
1
Bit 2
0
0
…
1
Bit 2
0
0
…
1
0
…
1
Bit 1
0
0
…
1
0
…
1
Bit 1
0
0
…
1
Bit 1
0
0
…
1
0
…
1
B
B
. When the value is from 0x80
. When the value is from 0x80
Bit 0
0
1
…
1
0
…
1
Bit 0
0
1
…
1
Bit 0
0
1
…
1
0
…
1
Data Sheet
Δt
0 ns
5 ns trailing
…
635 ns trailing
640 ns leading
…
5 ns leading
Δt
0
5
…
1275
Δt
0 ns
5 ns trailing
…
635 ns trailing
640 ns leading
…
5 ns leading
5
6
7
(ns)