ADP2380-EVALZ Analog Devices, ADP2380-EVALZ Datasheet - Page 18

• Manufacturer Part Number: ADP2380-EVALZ
• Description: Power Management IC Development Tools 20V 4A Evaluation Board
• Manufacturer: Analog Devices
• Type: DC/DC Converters, Regulators & Controllersr
• Series: ADP2380r

Specifications of ADP2380-EVALZ

• Rohs: yes
• Tool Is For Evaluation Of: ADP2380
• Input Voltage: 4.5 V to 20 V
• Factory Pack Quantity: 1

ADP2380
PROGRAMMING INPUT VOLTAGE UVLO
The internal voltage divider from PVIN to GND sets the default
start/stop values of the input voltage to achieve undervoltage
lockout (UVLO) performance. The default rising/falling threshold
of PVIN and UVLO are listed in Table 9. For a more accurate,
externally adjustable UVLO, these default values can be replaced
by using an external voltage divider, as shown in Figure 32.
Lower values of the external resistors are recommended to obtain
a high accuracy UVLO threshold because the values of the internal
320 kΩ and 125 kΩ resistors may vary by as much as 20%.
Table 9. Default Rising/Falling Voltage Threshold
Pin
PVIN
UVLO
A 1 kΩ resistor is an appropriate choice for R2. Use the following
equation to obtain the value of R1 for a chosen input voltage
rising threshold:
where V
The falling threshold of V
where V
COMPENSATION DESIGN
The
for excellent load and line transient response. For peak current
mode control, the power stage can be simplified as a voltage
controlled current source, supplying current to the output
capacitor and load resistor. It consists of one domain pole and
one zero contributed by the output capacitor ESR.
ADP2380
V
R1
IN
=
IN_RISING
IN_FALLING
_
FALLING
(
V
Rising Threshold (V)
4.28
1.2
IN
_
uses a peak current mode control architecture
Figure 32. External Programmable UVLO
RISING
is the rising threshold of V
V
is the falling threshold of V
=
IN
1
R1
R2
1
2 .
−
1 .
1
V
V
2 .
R2
×
V
IN
)
R1
can be determined by
×
PVIN
UVLO
R2
+
ADP2380
1
1 .
320kΩ
125kΩ
V
Falling Threshold (V)
3.92
1.1
IN
.
IN
.
Rev. 0 | Page 18 of 28
The control to output transfer function is given by
where:
A
R is the load resistance.
C
R
The external voltage loop is compensated by a transconductance
amplifier with a simple external RC network placed either between
COMP and GND or between COMP and FB, as shown in
Figure 33 and Figure 34, respectively.
Compensation Network Between COMP and GND
Figure 33 shows the simplified peak current mode control,
small signal circuit with a compensation network placed
between COMP and GND.
The R
and the optional C
The closed-loop transfer function is as follows:
Figure 33. Small Signal Circuit with Compensation Network Between COMP
OUT
ESR
VI
R
R
= 8.7 A/V.
TOP
BOT
is the equivalent series resistance of the output capacitor.
T
G
is the output capacitance.
V
f
f
V
C
OUT
P
Z
VD
) (
and C
s
=
=
(
2
s
2
FB
=
)
×
ADP2380
×
R
=
GND
π
π
BOT
C
V
+
V
–
×
R
g
×
compensation components contribute a zero,
COMP
m
BOT
OUT
+
(
R
R
R
ESR
CP
1
TOP
+
(
(
s
and R
1
s
R
)
×
×
)
COMP
ESR
C
C
C
R
=
C
C
C
OUT
−
A
)
+
g
×
C
VI
C
m
and GND
C
contribute an optional pole.
V
CP
×
COMP
OUT
R
×
C
×
s
CP
×

 


 

1
1
1
+
+
+
–
+
1
+
R
2
2
R
C
C
×
×
A
C
×
C
π
π
VI
×
C
+
s
s
C
×
×
C
C
C
×
CP
f
f
C
R
Data Sheet
×
C
Z
P
OUT
ESR
s
CP

 

×
s

 

×
R
G
V
OUT
VD
) (
s