IS42S16160D-7BLI-TR ISSI, Integrated Silicon Solution Inc, IS42S16160D-7BLI-TR Datasheet - Page 25

• Manufacturer Part Number: IS42S16160D-7BLI-TR
• Description: IC SDRAM 256MBIT 143MHZ 54BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16160D-7BLI-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-BGA
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6.5/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S83200D, IS42S16160D
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length deter-
mines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burst is available for the sequential type. The full-page
burst is used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.All
accesses for that burst take place within this block, mean-
BURST DEFINITION
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
12/12/07
Length
Burst
Page
Full
(y)
2
4
8
n = A0-A8 (x16)
n = A0-A9 (x8)
(location 0-y)
A 2
0
0
0
0
1
1
1
1
Starting Column
Address
A 1
A 1
0
0
1
1
0
0
1
0
0
1
1
1
A 0
A 0
A 0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
Type = Sequential
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A8 (x16) or
A1-A9 (x8) when the burst length is set to two; by A2-A8
(x16) or A2-A9 (x8) when the burst length is set to four;
and by A3-A8 (x16) or A3-A9 (x8) when the burst length
is set to eight. The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. Full-page bursts wrap within the page if the
boundary is reached.
the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.
Order of Accesses Within a Burst
Type = Interleaved
0-1-2-3-4-5-6-7
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
1-0-3-2-5-4-7-6
Not Supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
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