IS42S16160D-7BLI-TR ISSI, Integrated Silicon Solution Inc, IS42S16160D-7BLI-TR Datasheet - Page 45

• Manufacturer Part Number: IS42S16160D-7BLI-TR
• Description: IC SDRAM 256MBIT 143MHZ 54BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16160D-7BLI-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-BGA
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6.5/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S83200D, IS42S16160D
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
12/12/07
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the time
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
INTERNAL
COMMAND
ADDRESS
CLOCK
COMMAND
INTERNAL
CKE
ADDRESS
CLK
DQ
CLOCK
CKE
CLK
DQ
READ
BANK a,
COL n
T0
NOP
T0
NOP
T1
WRITE
BANK a,
COL n
D
T1
IN
n
NOP
T2
D
OUT
n
T2
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH;
the internal clock and related operation will resume on the
subsequent positive clock edge.
T3
D
T3
OUT
n+1
NOP
T4
D
NOP
IN
T4
n+1
NOP
D
T5
OUT
D
DON'T CARE
n+2
NOP
IN
T5
n+2
DON'T CARE
NOP
D
T6
OUT
n+3
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