M45PE10-VMN6P NUMONYX, M45PE10-VMN6P Datasheet - Page 17

• Manufacturer Part Number: M45PE10-VMN6P
• Description: IC FLASH 1MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE10-VMN6P

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Frequency: 75MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Base Number: 45
• Frequency: 75MHz
• Ic Generic Number: 45PE10
• Memory Configuration: 128K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M45PE10
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on serial data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ) or
read status register (RDSR) instruction, the shifted-in instruction sequence is followed by a
data-out sequence. Chip Select (S) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a page write (PW), page program (PP), page erase (PE), sector erase (SE),
write enable (WREN), write disable (WRDI), deep power-down (DP) or release from deep
power-down (RDP) instruction, Chip Select (S) must be driven High exactly at a byte
boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses after Chip Select (S) being driven Low is
an exact multiple of eight.
All attempts to access the memory array during a write cycle, program cycle or erase cycle
are ignored, and the internal write cycle, program cycle or erase cycle continues unaffected.
Table 3.
FAST_READ
Instruction
WREN
RDSR
READ
WRDI
RDID
RDP
PW
PP
PE
SE
DP
Instruction set
Write enable
Write disable
Read identification
Read status register
Read data bytes
Read data bytes at higher
speed
Page write
Page program
Page erase
Sector erase
Deep power-down
Release from deep
power-down
Description
Table
3.
One-byte instruction
0000 0110
0000 0100
1001 1111
0000 0101
0000 0011
0000 1011
0000 1010
0000 0010
1101 1011
1101 1000
1011 1001
1010 1011
code
DBh
D8h
ABh
9Fh
0Bh
0Ah
B9h
06h
04h
05h
03h
02h
Address
bytes
0
0
0
0
3
3
3
3
3
3
0
0
Dummy
bytes
0
0
0
0
0
1
0
0
0
0
0
0
Instructions
1 to 256
1 to 256
bytes
1 to ∞
1 to ∞
1 to ∞
1 to 3
Data
0
0
0
0
0
0
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