M45PE20-VMP6G NUMONYX, M45PE20-VMP6G Datasheet - Page 6

• Manufacturer Part Number: M45PE20-VMP6G
• Description: IC FLASH 2MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE20-VMP6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Memory Configuration: 256K X 8
• Ic Interface Type: Serial, SPI
• Clock Frequency: 25MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: VDFPN
• No. Of Pins: 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M45PE20
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Read,
Program, Erase or Write cycle is in progress, the
device will be in the Standby Power mode (this is
not the Deep Power-down mode). Driving Chip
Select (S) Low selects the device, placing it in the
Active Power mode.
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After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Reset (Reset). The Reset (Reset) input provides
a hardware reset for the memory. In this mode, the
outputs are high impedance.
When Reset (Reset) is driven High, the memory is
in the normal operating mode. When Reset (Re-
set) is driven Low, the memory will enter the Reset
mode, provided that no internal operation is cur-
rently in progress. Driving Reset (Reset) Low while
an internal operation is in progress has no effect
on that internal operation (a write cycle, program
cycle, or erase cycle).
Write Protect (W). This input signal puts the de-
vice in the Hardware Protected mode, when Write
Protect (W) is connected to V
256 pages of memory to become read-only by pro-
tecting them from write, program and erase oper-
ations. When Write Protect (W) is connected to
V
the other pages of memory.
CC
, the first 256 pages of memory behave like
SS
, causing the first