M45PE40-VMW6TG NUMONYX, M45PE40-VMW6TG Datasheet - Page 29

• Manufacturer Part Number: M45PE40-VMW6TG
• Description: IC FLASH 4MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE40-VMW6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M45PE40-VMW6TGTR

M45PE40
6.10
Sector erase (SE)
The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it
can be accepted, a write enable (WREN) instruction must previously have been executed.
After the write enable (WREN) instruction has been decoded, the device sets the write
enable latch (WEL).
The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on serial data input (D). Any address inside the
sector (see
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed sector erase cycle (whose duration is t
initiated. While the sector erase cycle is in progress, the status register may be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is complete, the write enable latch (WEL) bit is reset.
A sector erase (SE) instruction applied to a sector that contains a page that is hardware
protected is not executed.
Any sector erase (SE) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 15. Sector erase (SE) instruction sequence
1. Address bits A23 to A19 are don’t care.
S
C
D
Table
2) is a valid address for the sector erase (SE) instruction. Chip Select (S)
0
1
2
Instruction
3
4
Figure
5
6
7
15.
MSB
23 22
8
9
24-bit address
2
29 30 31
1
0
AI03751D
SE
Instructions
) is
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