M25P32-VMF6P NUMONYX, M25P32-VMF6P Datasheet - Page 29

• Manufacturer Part Number: M25P32-VMF6P
• Description: IC FLASH 32MBIT 75MHZ 16SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P32-VMF6P

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC
• Package: 16SO W
• Cell Type: NOR
• Density: 32 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 64KByte x 64
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3597; 497-3597

6.8
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
1. Address bits A23 to A22 are Don’t Care.
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data Input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
S
C
D
Q
S
C
D
Q
and data-out sequence
0
7
32 33 34
1
6
High Impedance
Dummy Byte
2
5
Instruction
3
4
35
4
3
36 37 38 39 40 41 42 43 44 45 46
2
5
1
6
0
7
MSB
23
7
8
22 21
Figure
6
9 10
24 BIT ADDRESS
DATA OUT 1
5
4
15.
3
28 29 30 31
3
2
2
1
1
0
0
47
MSB
7
6
DATA OUT 2
5
4
3
2
1
0
MSB
AI04006
7
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