M25PX64-VME6TG NUMONYX, M25PX64-VME6TG Datasheet - Page 26
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M25PX64-VME6TG
Manufacturer Part Number
M25PX64-VME6TG
Description
IC FLASH 64MBIT 75MHZ 8VDFPN
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25PX64-VME6TG.pdf
(70 pages)
Specifications of M25PX64-VME6TG
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
64M (8M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VDFPN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25PX64-VME6TGTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25PX64-VME6TG
Manufacturer:
NUMONYX
Quantity:
4 000
6
Note:
26/70
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C)
after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to
the device, most significant bit first, on serial data input(s) DQ0 (DQ1), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ),
dual output fast read (DOFR), read OTP (ROTP), read lock registers (RDLR), read status
register (RDSR), read identification (RDID) or release from deep power-down (RDP)
instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip
Select (S) can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a page program (PP), program OTP (POTP), dual input fast program (DIFP),
subsector erase (SSE), sector erase (SE), bulk erase (BE), write status register (WRSR),
write to lock register (WRLR), write enable (WREN), write disable (WRDI) or deep power-
down (DP) instruction, Chip Select (S) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must
driven High when the number of clock pulses after Chip Select (S) being driven Low is an
exact multiple of eight.
All attempts to access the memory array during a write status register cycle, program cycle
or erase cycle are ignored, and the internal write status register cycle, program cycle or
erase cycle continues unaffected.
Output Hi-Z is defined as the point where data out is no longer driven.
Table
5.