M25PX64-VME6G NUMONYX, M25PX64-VME6G Datasheet
M25PX64-VME6G
Specifications of M25PX64-VME6G
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M25PX64-VME6G Summary of contents
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... More than 20 years data retention Packages – RoHS compliant November 2009 64-Mbit, dual I/O, 4-Kbyte subsector erase, VDFPN8 (ME) 8 × (MLP8) SO16 (MF) 300 mils width Automotive Certified Parts Available Rev 10 M25PX64 VDFPN8 (MD) 8 × (MLP8) (with reduced D2 dimension) TBGA24 (ZM) 6x8 mm 1/70 www.numonyx.com 1 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Read status register (RDSR ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description The M25PX64 is a 64-Mbit (8 Mbits x 8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25PX64 supports two new, high-performance dual input/output instructions: Dual output fast read (DOFR) instruction used to read data MHz by using ...
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... There is an exposed central pad on the underside of the VDFPN8 package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See section for package dimensions, and how to identify pin-1. Package mechanical V CC DQ1 M25PX64 V SS AI14228b Function M25PX64 DQ1 2 7 HOLD W ...
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... Figure 3. SO16 connections don’t use. 2. See Package mechanical Figure 4. BGA 6x8 24 ball ballout Note Connection 2 See Section 11: Package 8/70 M25PX64 HOLD DQ0 DQ1 8 9 W/V section for package dimensions, and how to identify pin-1. mechanical. PP AI13721c ...
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Signal descriptions 2.1 Serial data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). During the dual input fast program (DIFP) ...
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Write protect/enhanced program supply voltage (W/V W/V is both a control input and a power supply pin. The two functions are selected by the PP voltage range applied to the pin. If the W/V input is kept in a ...
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... Resistors R (represented in ensure that the M25PX64 is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all inputs/outputs are in high ...
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Example pF, that is R*C p master never leaves the SPI bus in the high impedance state for a time period shorter than 5 μs. Figure 6. SPI modes supported CPOL CPHA ...
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Operating features 4.1 Page programming To program one data byte, two instructions are required: write enable (WREN), which is one byte, and a page program (PP) sequence, which consists of four bytes plus data. This is followed by the ...
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When Chip Select (S) is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). The device then goes in to the standby power mode. The ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PX64 features the following data protection mechanisms: Power on reset and an internal timer (t changes while the power supply is outside the operating specification ...
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Specific hardware and software protection There are two software protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. The SPM2 can be locked by hardware with the help of the W input ...
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Table 3. Protected area sizes Status register contents bit bit 2 bit 1 bit none Upper 64th (2 sectors: 126 and 127 Upper ...
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Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any write status register, program or erase cycle that is ...
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Memory organization The memory is organized as: 8 388 608 bytes (8 bits each) 2048 subsectors (4 Kbytes each) 128 sectors (64 Kbytes each) 32768 pages (256 bytes each) 64 OTP bytes located outside the main memory array. Each ...
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Table 4. Memory organization Sector Subsector 2047 127 2032 2031 126 2016 2015 125 2000 1999 124 1984 1983 123 1968 1967 122 1952 1951 121 1936 1935 120 1920 1919 119 1904 1903 118 1888 1887 117 1872 20/70 ...
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Table 4. Memory organization (continued) Sector Subsector Address range 1695 69F000h 105 1680 690000h 1679 68F000h 104 1664 680000h 1663 67F000h 103 1648 670000h 1647 66F000h 102 1632 660000h 1631 65F000h 101 1616 650000h 1615 64F000h 100 1600 640000h 1599 ...
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Table 4. Memory organization (continued) Sector Subsector 1343 83 1328 1327 82 1312 1311 81 1296 1295 80 1280 1279 79 1264 1263 78 1248 1247 77 1232 1231 76 1216 1215 75 1200 1199 74 1184 1183 73 1168 ...
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Table 4. Memory organization (continued) Sector Subsector Address range 991 3DF000h 61 976 3D0000h 975 3CF000h 60 960 3C0000h 959 3BF000h 59 944 3B0000h 943 3AF000g 58 928 3A0000h 927 39F000h 57 912 390000h 911 38F000h 56 896 380000h 895 ...
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Table 4. Memory organization (continued) Sector Subsector 639 39 624 623 38 608 607 37 592 591 36 576 575 35 560 559 34 544 543 33 528 527 32 512 511 31 496 495 30 480 479 29 464 ...
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Table 4. Memory organization (continued) Sector Subsector Address range 287 11F000h 17 272 110000h 271 10F000h 16 256 100000h 255 FF000h 15 240 F0000h 239 EF000h 14 224 E0000h 223 DF000h 13 208 D0000h 207 CF000h 12 192 C0000h 191 ...
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Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C) after Chip Select (S) ...
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Table 5. Instruction set Instruction Description WREN Write enable WRDI Write disable RDID Read identification RDSR Read status register WRSR Write status register WRLR Write to lock register RDLR Read lock register READ Read data bytes FAST_READ Read data bytes ...
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Write enable (WREN) The write enable (WREN) instruction The write enable latch (WEL) bit must be set prior to every page program (PP), dual input fast program (DIFP), program OTP (POTP), write to lock register (WRLR), subsector erase (SSE), ...
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Write disable (WRDI) The write disable (WRDI) instruction The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The write enable latch (WEL) bit is ...
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... Device identification (2 bytes) A unique ID code (UID) (17 bytes, of which 16 available upon customer request). The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (71h), and the memory capacity of the device in the second byte (17h). ...
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Figure 11. Read identification (RDID) instruction sequence and data-out sequence 31/70 ...
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Read status register (RDSR) The read status register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase or write status register cycle is in progress. ...
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Top/bottom bit The top/bottom (TB) bit is non-volatile. It can be set and reset with the write status register (WRSR) instruction provided that the write enable (WREN) instruction has been issued. The top/bottom (TB) bit is used in conjunction ...
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Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable ...
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Table 8. Protection modes W/V SRWD PP Mode signal bit Software protected (SPM Hardware 0 1 protected (HPM defined by the values in the block protect (BP2, BP1, BP0) bits of the ...
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Read data bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising ...
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Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) ...
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Dual output fast read (DOFR) The dual output fast read (DOFR) instruction is very similar to the read data bytes at higher speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin DQ0 and pin ...
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Read lock register (RDLR) The device is first selected by driving Chip Select (S) Low. The instruction code for the read lock register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned ...
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Read OTP (ROTP) The device is first selected by driving Chip Select (S) Low. The instruction code for the read OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each bit is latched ...
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Page program (PP) The page program (PP) instruction allows bytes to be programmed in the memory (changing bits from ‘1’ to ‘0’). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the ...
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Figure 19. Page program (PP) instruction sequence DQ0 Data byte DQ0 MSB 1. Address bit A23 is don’t care. 42/ ...
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Dual input fast program (DIFP) The dual input fast program (DIFP) instruction is very similar to the page program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. ...
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Figure 20. Dual input fast program (DIFP) instruction sequence Instruction DQ0 DQ1 DQ0 DATA DQ1 MSB 1. Address bit A23 ...
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Program OTP instruction (POTP) The program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from ‘1’ to ‘0’, only). Before it can be accepted, a write enable (WREN) ...
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Figure 21. Program OTP (POTP) instruction sequence DQ0 Data byte DQ0 MSB 1. A23 to A7 are don't care ≤ n ≤ 65. Figure 22. ...
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Write to lock register (WRLR) The write to lock register (WRLR) instruction allows bits to be changed in the lock registers. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write ...
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Subsector erase (SSE) The subsector erase (SSE) instruction sets to ‘1’ (FFh) all bits inside the chosen subsector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction ...
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Sector erase (SE) The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction ...
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Bulk erase (BE) The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the ...
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Deep power-down (DP) Executing the deep power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). It can also be used as a software protection mechanism, while the device ...
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Release from deep power-down (RDP) Once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down (RDP) instruction. Executing this instruction takes the device out of the deep power-down mode. The ...
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Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at power-up, and then for a further delay ...
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Figure 29. Power-up timing (max (min) Reset state of the device V WI Table 11. Power-up timing and V Symbol ( (min Low VSL CC (1) t Time delay to ...
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... These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE program and other relevant quality documents. Table 12. ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the ...
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Table 16. Capacitance Symbol Parameter C Input/output capacitance (DQ0/DQ1) IN/OUT C Input capacitance (other pins Sampled only, not 100% tested Table 17. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current ...
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Table 18. AC characteristics Symbol Alt. Clock frequency for the following instructions: DOFR, DIFP, FAST_READ SSE, SE, BE, DP, WREN, WRDI, RDID RDSR, WRSR, ROTP, PP, POTP, WRLR, RDLR, RDP f Clock frequency for read instructions ...
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Table 18. AC characteristics (continued) Test conditions specified in Symbol Alt. Parameter t Write status register cycle time W Page program cycle time (256 bytes) (7) t Page program cycle time (n bytes) PP Program OTP cycle time (64 bytes) ...
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Figure 32. Write protect setup and hold timing during WRSR when SRWD=1 W/V PP tWHSL S C DQ0 DQ1 Figure 33. Hold timing S C DQ1 DQ0 HOLD 60/70 High Impedance tHLCH tCHHL tCHHH tHLQZ tSHWL AI07439c tHHCH tHHQX AI13746 ...
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Figure 34. Output timing S C tCLQV tCLQX tCLQX DQ1 ADDR. DQ0 LSB IN Figure 35. V timing PPH S C DQ0 V PPH V PP tVPPHSL tCH tCLQV tCL tQLQH tQHQL End of command (identified by WIP polling) tSHQZ ...
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... Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Figure 37. VDFPN8 (MLP8, MD) 8-lead very thin dual flat package no lead, 8 × 6 mm, package outline Drawing is not to scale. 2. The circle in the top view of the package indicates the ...
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Figure 38. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline SO-H 1. Drawing is not to scale. Table 21. SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data Symbol Typ A ...
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Figure 39. TBGA, 6x8 mm, 24 ball package outline 65/70 ...
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Table 22. TBGA 6x8 mm 24-ball package dimensions MIN A A1 0.20 A2 Øb 0. balls aaa bbb ddd eee fff Control unit: mm ...
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... T = Tape and reel packing Plating Technology RoHS compliant Lithography B = 110nm, Fab.2 Diffusion Plant blank = 110 nm Automotive Grade ( Automotive –40 to 125 °C Part. Device tested with high reliability certified flow. blank = standard – °C device 1. Secure options are available upon customer request. M25PX64 – ( 67/70 ...
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... Numonyx strongly recommends the use of the Automotive Grade devices(AutoGrade 6 and Grade 3) for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. 3. Device grade 3 available in an SO8 RoHS compliant package. Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx sales office ...
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... Initial release. Updated the minimum value for t SHSL Applied Numonyx branding. Corrected bulk erase specifications on the cover page. Added the following information regarding Bulk Erase: Avoid applying V the W/VPP pin during Bulk Erase. Added the TBGA package and accompanying informaiton. ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...