M25PX64-VZM6TP NUMONYX, M25PX64-VZM6TP Datasheet - Page 48

• Manufacturer Part Number: M25PX64-VZM6TP
• Description: IC FLASH 64MBIT 75MHZ 24TBGA
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PX64-VZM6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (8M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PX64-VZM6TPTR

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Subsector erase (SSE)
The subsector erase (SSE) instruction sets to ‘1’ (FFh) all bits inside the chosen subsector.
Before it can be accepted, a write enable (WREN) instruction must previously have been
executed. After the write enable (WREN) instruction has been decoded, the device sets the
write enable latch (WEL).
The subsector erase (SSE) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, and three address bytes on serial data input (DQ0). Any address inside
the subsector (see
Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the subsector erase (SSE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed subsector erase cycle (whose duration is t
initiated. While the subsector erase cycle is in progress, the status register may be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed subsector erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the write enable latch (WEL) bit is reset.
A subsector erase (SSE) instruction issued to a sector that is hardware or software
protected, is not executed.
Any subsector erase (SSE) instruction, while an erase, program or write cycle is in progress,
is rejected without having any effects on the cycle that is in progress.
Figure 24. Subsector erase (SSE) instruction sequence
1. Address bit A23 is don’t care.
S
C
DQ0
Table
0
4) is a valid address for the subsector erase (SSE) instruction.
1
2
Instruction
3
4
Figure
5
6
7
24.
MSB
23 22
8
9
24-bit address
2
29 30 31
(1)
1
0
AI13741b
SSE
) is