CY62128EV30LL-45SXI Cypress Semiconductor Corp, CY62128EV30LL-45SXI Datasheet - Page 5

IC SRAM 1MBIT 45NS 32SOIC

CY62128EV30LL-45SXI

Manufacturer Part Number
CY62128EV30LL-45SXI
Description
IC SRAM 1MBIT 45NS 32SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr
Datasheet

Specifications of CY62128EV30LL-45SXI

Memory Size
1M (128K x 8)
Package / Case
32-SOIC (11.30mm Width)
Format - Memory
RAM
Memory Type
SRAM
Speed
45ns
Interface
Parallel
Voltage - Supply
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Access Time
45 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.2 V
Maximum Operating Current
16 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
2.5 V, 3.3 V
Memory Configuration
128K X 8
Supply Voltage Range
2.2V To 3.6V
Memory Case Style
SOIC
No. Of Pins
32
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2065-5
CY62128EV30LL-45SXI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62128EV30LL-45SXI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY62128EV30LL-45SXIT
Manufacturer:
CYPRESS/PBF
Quantity:
587
Capacitance
Thermal Resistance
Data Retention Characteristics
(Over the Operating Range)
Note
Document #: 38-05579 Rev. *I
C
C
V
I
t
t
Parameter
Parameter
9. Tested initially and after any design or process changes that may affect these parameters.
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
11. Chip enables (CE
12. Full device AC operation requires linear V
CCDR
CDR
R
Parameter
DR
IN
OUT
[12]
[9]
[11]
JA
JC
OUTPUT
INCLUDING
[9]
[9]
V
JIG AND
CC
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
SCOPE
V
Data retention current
Chip deselect to data retention time
Operation recovery time
Input capacitance
Output capacitance
CC
1
30 pF
and CE
for data retention
Parameters
Description
Description
R
V
R1
R1
R2
2
TH
TH
) must be at CMOS level to meet the I
Description
R2
CC
Equivalent to:
ramp from V
Still air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
T
V
A
CC
Figure 4. AC Test Loads and Waveforms
= 25 °C, f = 1 MHz,
= V
OUTPUT
CC(typ)
DR
Test Conditions
Test Conditions
V
CE
V
to V
CC
IN
Rise Time = 1 V/ns
1
CC(min)
> V
SB2
> V
= 1.5 V,
THEVENIN
/ I
CC
CC
CCDR
> 100 µs or stable at V
16667
15385
GND
2.50V
8000
 0.2 V or CE
0.2 V or V
1.20
V
CC
spec. Other inputs can be left floating.
EQUIVALENT
R
TH
10%
Conditions
IN
2
ALL INPUT PULSES
< 0.2 V
< 0.2 V,
CC(min)
V
TSOP I
90%
33.01
3.42
 100 µs.
1103
1554
Max
3.0V
1.75
645
10
10
Industrial
CC
25.86
SOIC
48.67
= V
CY62128EV30 MoBL
90%
CC(typ)
10%
Fall Time = 1 V/ns
, T
A
Min
1.5
45
= 25 °C.
0
STSOP
32.56
3.59
Typ
Unit
Unit
[10]
pF
pF
V
Page 5 of 15
Max Unit
3
°C/W
°C/W
Unit
µA
ns
ns
V
®
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