CY62128EV30LL-45SXI Cypress Semiconductor Corp, CY62128EV30LL-45SXI Datasheet - Page 7

• Manufacturer Part Number: CY62128EV30LL-45SXI
• Description: IC SRAM 1MBIT 45NS 32SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62128EV30LL-45SXI

• Memory Size: 1M (128K x 8)
• Package / Case: 32-SOIC (11.30mm Width)
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 16 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V, 3.3 V
• Memory Configuration: 128K X 8
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2065-5; CY62128EV30LL-45SXI

Switching Waveforms
Notes
Document #: 38-05579 Rev. *I
18. The internal write time of the memory is defined by the overlap of WE, CE = V
19. The device is continuously selected. OE, CE
20. WE is HIGH for read cycle.
21. CE is the logical combination of CE
22. Address valid before or similar to CE
23. Data I/O is high impedance if OE = V
24. If CE
25. During this period, the I/Os are in output state. Do not apply input signals.
DATA OUT
CURRENT
ADDRESS
DATA OUT
ADDRESS
ADDRESS
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
SUPPLY
DATA I/O
1
V
CE
OE
goes HIGH or CE
CC
WE
OE
CE
NOTE
2
PREVIOUS DATA VALID
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
25
HIGH IMPEDANCE
t
PU
1
t
1
Figure 6. Read Cycle 1 Address transition controlled
and CE
IH
LZCE
t
SA
transition LOW and CE
.
t
HZOE
Figure 8. Write Cycle No. 1 WE controlled
Figure 7. Read Cycle No. 2 OE controlled
t
t
ACE
LZOE
1
2
. When CE
= V
t
OHA
50%
IL
t
DOE
, CE
2
1
= V
is LOW and CE
t
IH
AA
2
t
.
AW
transition HIGH.
t
t
SCE
RC
2
t
WC
is HIGH, CE is LOW; when CE
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
t
RC
RC
t
t
PWE
DATA VALID
SD
DATA VALID
[18, 21, 23, 24]
[20, 21, 22]
1
is HIGH or CE
[19, 20]
DATA VALID
t
t
HZOE
HA
CY62128EV30 MoBL
t
HD
2
t
is LOW, CE is HIGH.
HZCE
t
PD
50%
IMPEDANCE
HIGH
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