RC28F128M29EWLA NUMONYX, RC28F128M29EWLA Datasheet - Page 19

• Manufacturer Part Number: RC28F128M29EWLA
• Description: IC FLASH 128MBIT 25NS 64BGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of RC28F128M29EWLA

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16Mx8, 8Mx16)
• Speed: 60ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Numonyx
3
3.1
3.2
3.3
3.4
®
Axcell™ M29EW
Bus Operations
There are four standard bus operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby.
See
summary. Typical glitches of less than 5ns on Chip Enable, Write Enable, and Reset pins
are ignored by the memory and do not affect bus operations.
Bus Read
Bus Read operations read from the memory cells, registers or CFI space. To speed up the
read operation the memory array can be read in Page mode where data is internally read
and stored in a page buffer. The page has a size of 8 words (or 16 bytes) and is addressed
by the address inputs A2-A0 in x16 bus mode and A2-A0 plus DQ15/A 1 in x8 bus mode.
The Extended Memory Blocks and CFI area do not support Page Read mode.
A valid Bus Read operation involves setting the desired address on the Address inputs,
applying a Low signal, V
High, V
waveforms (8-bit
Read AC characteristics (Sheet of
Bus Write
Bus Write operations write to the command interface. A valid Bus Write operation begins by
setting the desired address on the Address inputs. The Address inputs are latched by the
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data inputs/outputs are latched by the command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the entire Bus Write operation. See
and
Output Disable
The Data inputs/outputs are in the high impedance state when Output Enable is High, V
Standby
Driving Chip Enable High in Read mode, causes the memory to enter Standby mode and
the data inputs/outputs pins are placed in the high-impedance state. To reduce the Supply
current to the Standby Supply current, I
For the Standby current level see
During program or erase operations the memory will continue to use the Program/Erase
Supply current, I
Table 24
Table 3: Bus operations, 8-bit mode
IH
. The Data inputs/outputs will output the value, see
and
CC3
mode),
Table
, for Program or Erase operations until the operation completes.
25, Write AC characteristics, for details of the timing requirements.
IL
Figure 23: Page Read AC waveforms (16-bit
, to Chip Enable and Output Enable and keeping Write Enable
Table 22: DC
208031-04
2), for details of when the output becomes valid.
CC2
and
Figure
, Chip Enable should be held within V
Table 4: Bus operations, 16-bit mode
characteristics.
24, and
Figure
Figure 20: Random Read AC
25, Write AC waveforms,
mode), and
Bus Operations
CC
Table 23:
for a
± 0.3 V.
IH
IH
19
.
,