CY62157EV30LL-45ZXI Cypress Semiconductor Corp, CY62157EV30LL-45ZXI Datasheet
CY62157EV30LL-45ZXI
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CY62157EV30LL-45ZXI
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CY62157EV30LL-45ZXI Summary of contents
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... Power Down Circuit Cypress Semiconductor Corporation Document #: 38-05445 Rev. *I 8-Mbit (512 K × 16) Static RAM Functional Description The CY62157EV30 is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life ...
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Contents Pin Configuration .............................................................3 Product Portfolio ..............................................................3 Maximum Ratings .............................................................4 Operating Range ...............................................................4 Electrical Characteristics .................................................4 Capacitance ......................................................................5 Thermal Resistance ..........................................................5 Data Retention Characteristics .......................................6 Data Retention Waveform ................................................6 Switching Characteristics ................................................7 Switching Waveforms ......................................................8 Read Cycle No. 1 (Address ...
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... A1 24 Product Portfolio Product Range CY62157EV30LL Industrial/Auto-A Auto-E Notes 1. NC pins are not connected on the die. 2. The 44-pin TSOP II package has only one chip enable (CE) pin. 3. The BYTE pin in the 48-pin TSOP I package must be tied HIGH to use the device as a 512 K × 16 SRAM. The 48-pin TSOP I package can also be used × 8 SRAM by tying the BYTE signal LOW ...
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... Document #: 38-05445 Rev. *I Output Current into Outputs (LOW) ............................20 mA Static Discharge Voltage ........................................> 2001 V (MIL-STD-883, Method 3015) Latch Up Current ...................................................> 200 mA Operating Range Device + 0.3 V) CY62157EV30LL Industrial/ CCmax + 0.3 V) CCmax + 0 max 45 ns (Industrial/ Auto-A) Test Conditions Min Typ = –0.1 mA 2.0 = – ...
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Capacitance [10] Parameter Description C Input capacitance IN C Output capacitance OUT Thermal Resistance [10] Parameter Description Thermal resistance JA (Junction to Ambient) Thermal resistance JC (Junction to Case OUTPUT 30 pF INCLUDING JIG AND ...
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... BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. Document #: 38-05445 Rev. *I Conditions = 1 > V – 0.2 V, Industrial/Auto < 0 Auto-E – 0 > V – 0 < 0 CY62157EV30LL-45 CY62157EV30LL-55 [15] Figure 5. Data Retention Waveform DATA RETENTION MODE > 1.5V V CC(min CDR > 100 s or stable at V > 100 CC(min) CC(min) ® CY62157EV30 MoBL [11] Min Typ Max Unit 1 ...
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... If both byte enables are toggled together, this value is 10 ns. 21. The internal write time of the memory is defined by the overlap of WE and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write ...
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Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled) ADDRESS BHE/BLE t LZBE OE HIGH IMPEDANCE DATA OUT t LZCE ...
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... HZOE Notes 25. The internal write time of the memory is defined by the overlap of WE write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 26. Data I/O is high impedance ...
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... HZOE Notes 29. The internal write time of the memory is defined by the overlap of WE write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 30. Data I/O is high impedance ...
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Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS BHE/BLE NOTE 34 DATA I/O t HZWE Notes 33 goes HIGH and CE goes LOW simultaneously with WE = ...
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Switching Waveforms (continued) Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) ADDRESS BHE/BLE NOTE 36 DATA I/O Notes 35 goes HIGH and CE goes LOW simultaneously with ...
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Truth Table BHE 1 2 [37 [37 [37] [37 ...
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... Ordering Information Speed (ns) Ordering Code 45 CY62157EV30LL-45BVI CY62157EV30LL-45BVXI CY62157EV30LL-45ZSXI CY62157EV30LL-45ZXI CY62157EV30LL-45BVXA CY62157EV30LL-45ZSXA CY62157EV30LL-45ZXA 55 CY62157EV30LL-55ZSXE CY62157EV30LL-55ZXE Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions 621 5 E V30 Document #: 38-05445 Rev. *I Package Package Type Diagram 51-85150 48-ball very fine-pitch ball grid array ...
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Package Diagrams Figure 6. 48-pin VFBGA (6 × 8 × 1 mm) BV48/BZ48, 51-85150 Document #: 38-05445 Rev. *I ® CY62157EV30 MoBL 51-85150 *F Page [+] Feedback ...
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Package Diagrams (continued) Document #: 38-05445 Rev. *I Figure 7. 44-pin TSOP Z44-II, 51-85087 ® CY62157EV30 MoBL 51-85087 *C Page [+] Feedback ...
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Package Diagrams (continued) Figure 8. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A, 51-85183 Document #: 38-05445 Rev. *I ® CY62157EV30 MoBL 51-85183 *B Page [+] Feedback ...
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... CMOS complementary metal oxide semiconductor I/O input/output OE output enable RAM random access memory SRAM static random access memory TSOP thin small outline package VFBGA very fine-pitch ball grid array WE write enable Document #: 38-05445 Rev. *I CY62157EV30 MoBL Document Conventions Units of Measure ...
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Document History Page Document Title: CY62157EV30 MoBL Document Number: 38-05445 Orig. of Submission Rev. ECN No. Change Date ** 202940 AJU See ECN *A 291272 SYT See ECN *B 444306 NXR See ECN *C 467052 NXR See ECN *D 925501 ...
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Document History Page (continued) Document Title: CY62157EV30 MoBL Document Number: 38-05445 Orig. of Submission Rev. ECN No. Change Date *F 2724889 NXR/AESA 06/26/09 *G 2927528 VKN 05/04/2010 Renamed “DNU” pins as “NC” for 48 TSOP I package *H 3110053 PRAS ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...