M48Z128Y-70PM1 STMicroelectronics, M48Z128Y-70PM1 Datasheet - Page 5

• Manufacturer Part Number: M48Z128Y-70PM1
• Description: IC NVSRAM 1MBIT 70NS 32DIP
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48Z128Y-70PM1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-DIP (600 mil) Module
• Data Bus Width: 8 bit
• Organization: 128 Kb x 8
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Operating Current: 105 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Word Size: 8b
• Density: 1Mb
• Access Time (max): 70ns
• Operating Supply Voltage (typ): 5V
• Package Type: PMDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Through Hole
• Supply Current: 105mA
• Memory Configuration: 128K X 8
• Nvram Features: Internal Battery
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: PMDIP
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2874-5

M48Z128, M48Z128Y, M48Z128V
1
Description
The M48Z128/Y/V ZEROPOWER
as131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM
and a control circuit in a plastic, 32-pin DIP module to provide a highly integrated battery-
backed memory solution.
The M48Z128/Y/V is a non-volatile pin and function equivalent to any JEDEC standard
128 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,
providing the non-volatility of PROMs without any requirement for special WRITE timing or
limitations on the number of WRITEs that can be performed. The 32-pin, 600 mil DIP
module houses the M48Z128/Y/V silicon with a long-life lithium button cell in a single
package.
Figure 1.
Table 1.
DQ0-DQ7
Logic diagram
Signal names
A0-A16
V
V
NC
W
G
E
CC
SS
A0-A16
W
G
Doc ID 2426 Rev 5
E
®
17
RAM is a 128 Kbit x 8 non-volatile static RAM organized
Address inputs
Data inputs / outputs
Chip enable input
Output enable input
WRITE enable input
Supply voltage
Ground
Not connected internally
V CC
M48Z128Y
M48Z128V
V SS
M48Z128
8
DQ0-DQ7
Description
AI01194
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