M48Z128Y-70PM1 STMicroelectronics, M48Z128Y-70PM1 Datasheet - Page 7

• Manufacturer Part Number: M48Z128Y-70PM1
• Description: IC NVSRAM 1MBIT 70NS 32DIP
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48Z128Y-70PM1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-DIP (600 mil) Module
• Data Bus Width: 8 bit
• Organization: 128 Kb x 8
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Operating Current: 105 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Word Size: 8b
• Density: 1Mb
• Access Time (max): 70ns
• Operating Supply Voltage (typ): 5V
• Package Type: PMDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Through Hole
• Supply Current: 105mA
• Memory Configuration: 128K X 8
• Nvram Features: Internal Battery
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: PMDIP
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2874-5

M48Z128, M48Z128Y, M48Z128V
2
Note:
2.1
Operating modes
The M48Z128/Y/V also has its own power-fail detect circuit. The control circuitry constantly
monitors the single V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
switchover voltage (V
until valid power returns.
Table 2.
1. See
X = V
READ mode
The M48Z128/Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
1,048,576 locations in the static storage array. Thus, the unique address specified by the 17
address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
address input signal is stable, providing that the E and G (output enable) access times are
also satisfied. If the E and G access times are not met, valid data will be available after the
later of chip enable access time (t
the eight three-state data I/O signals is controlled by E and G. If the outputs are activated
before t
inputs are changed while E and G remain low, output data will remain valid for output data
hold time (t
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
IH
Table 10 on page 15
AVQV
or V
AXQX
IL
, the data lines will be driven to an indeterminate state until t
V
Operating modes
; V
SO
4.75 to 5.5 V
) but will go indeterminate until the next address access.
SO
4.5 to 5.5 V
3.0 to 3.6 V
to V
≤ V
= battery backup switchover voltage.
V
PFD
or
or
SO
CC
CC
SO
(1)
), the control circuitry connects the battery which maintains data
for details.
(min)
supply for an out of tolerance condition. When V
(1)
Doc ID 2426 Rev 5
ELQV
V
V
V
V
E
X
X
IH
IL
IL
IL
) or output enable access time (t
V
V
G
X
X
X
X
IH
IL
V
V
V
W
X
X
X
IH
IH
IL
DQ0-DQ7
CC
High Z
High Z
High Z
High Z
D
D
OUT
. As V
IN
AVQV
CC
) after the last
Battery backup mode
GLQV
AVQV
falls below the
CC
Operating modes
CMOS standby
is out of
). The state of
. If the address
Standby
Power
Active
Active
Active
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