AT49BV4096A-12TI Atmel, AT49BV4096A-12TI Datasheet - Page 3

• Manufacturer Part Number: AT49BV4096A-12TI
• Description: IC FLASH 4MBIT 120NS 48TSOP
• Manufacturer: Atmel

Specifications of AT49BV4096A-12TI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8 or 256K x 16)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AT49BV004(T) Block Diagram
AT49BV4096A(T) Block Diagram
Device Operation
READ: The AT49BV004(T)/4096A(T) is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
ADDRESS
ADDRESS
INPUTS
INPUTS
RESET
RESET
GND
GND
V CC
V PP
VCC
VPP
WE
WE
OE
CE
OE
CE
Y DECODER
X DECODER
Y DECODER
X DECODER
CONTROL
CONTROL
LOGIC
LOGIC
DATA INPUTS/OUTPUTS
DATA INPUTS/OUTPUTS
I/O0 - I/O7 – I/O0 - I/O15
PROGRAM DATA
PROGRAM DATA
INPUT/OUTPUT
MAIN MEMORY
INPUT/OUTPUT
(240K WORDS)
MAIN MEMORY
PARAMETER
PARAMETER
(480K BYTES)
BOOT BLOCK
PARAMETER
PARAMETER
BOOT BLOCK
4K WORDS
4K WORDS
I/O0 - I/O7
LATCHES
Y-GATING
8K WORDS
BUFFERS
BUFFERS
LATCHES
Y-GATING
8K BYTES
8K BYTES
16K BYTES
BLOCK 2
BLOCK 1
BLOCK 2
BLOCK 1
AT49BV4096A
AT49BV004
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
3FFFF
03FFF
02FFF
01FFF
00000
04000
03000
02000
7FFFF
07FFF
05FFF
03FFF
00000
06000
08000
04000
DATA INPUTS/OUTPUTS
DATA INPUTS/OUTPUTS
I/O0 - I/O7 – I/O0 - I/O15
PROGRAM DATA
PROGRAM DATA
INPUT/OUTPUT
INPUT/OUTPUT
MAIN MEMORY
(240K WORDS)
BOOT BLOCK
MAIN MEMORY
PARAMETER
PARAMETER
BOOT BLOCK
PARAMETER
PARAMETER
I/O0 - I/O7
4K WORDS
4K WORDS
8K WORDS
480K BYTES
16K BYTES
BUFFERS
LATCHES
Y-GATING
Y-GATING
8K BYTES
8K BYTES
BUFFERS
LATCHES
BLOCK 1
BLOCK 2
BLOCK 1
BLOCK 2
AT49BV4096AT
AT49BV004T
3FFFF
3DFFF
3CFFF
3BFFF
3E000
3D000
3C000
00000
7FFFF
7BFFF
7C000
7A000
79FFF
77FFF
00000
78000
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