AT49BV8192A-90TC Atmel, AT49BV8192A-90TC Datasheet - Page 6

• Manufacturer Part Number: AT49BV8192A-90TC
• Description: IC FLASH 8MBIT 90NS 48TSOP
• Manufacturer: Atmel

Specifications of AT49BV8192A-90TC

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT49BV8192A90TC

TOGGLE BIT: In addition to Data Polling, the AT49BV/LV008A(T)/8192A(T) provides
another method for determining the end of a program or erase cycle. During a program
or erase operation, successive attempts to read data from the device will result in I/O6
toggling between one and zero. Once the program cycle has completed, I/O6 will stop
toggling and valid data will be read. Examining the toggle bit may begin at any time dur-
ing a program cycle.
READY/BUSY: For the AT49BV/LV008A(T), pin 12 is an open-drain Ready/Busy output
pin that provides another method of detecting the end of a program or erase operation.
RDY/BUSY is actively pulled low during the internal program and erase cycles and it is
released at the completion of the cycle. The open-drain connection allows for OR-tying
of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro-
grams to the AT49BV/LV008A(T)/8192A(T) in the following ways: (a) V
sense: if V
CC
CC
is below 1.8V (typical), the program function is inhibited. (b) V
power on delay: once
CC
V
has reached the V
sense level, the device will automatically time-out 10 ms (typi-
CC
CC
cal) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE
high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs
and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely
affecting the operation of the device. The I/O lines can only be driven from 0 to V
+
CC
0.6V.
AT49BV/LV008A(T) ALTERNATE PIN DEFINITION: Two AT49BV/LV008A(T) BGA pin
definitions are shown. The standard pin definition allows use of the JEDEC standard
programming algorithm. If the alternate pin definition is used, the programming algo-
rithm must be modified as shown in the Command Definition for Alternate Pin Definition
table on page 8.
AT49BV/LV008A(T)/8192A(T)
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1049K–FLASH–11/02