AT45DB161D-SU Atmel, AT45DB161D-SU Datasheet - Page 51

IC FLASH 16MBIT 66MHZ 8SOIC

AT45DB161D-SU

Manufacturer Part Number
AT45DB161D-SU
Description
IC FLASH 16MBIT 66MHZ 8SOIC
Manufacturer
Atmel

Specifications of AT45DB161D-SU

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
16M (4096 pages x 528 bytes)
Speed
66MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Architecture
Sectored
Interface Type
SPI
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
15 mA
Mounting Style
SMD/SMT
Organization
128 KB x 16
Current, Input, Leakage
1 μA
Current, Operating
11 mA (Read), 12 mA (Program/Erase)
Current, Output, Leakage
1
Data Retention
20 yrs.
Density
16M
Package Type
EIAJ SOIC
Temperature, Operating
-40 to +85 °C
Time, Access
6 ns
Time, Address Hold
5
Time, Address Setup
5
Time, Fall
6.8 ns
Time, Rise
6.8 ns
Voltage, Input, High
1.89 to 2.52 V
Voltage, Input, Low
0.81 to 1.08 V
Voltage, Output, High
2.5 V
Voltage, Output, Low
0.4 V
Voltage, Supply
2.7 to 3.6 V
Memory Configuration
4096 Pages X 528 Bytes
Clock Frequency
66MHz
Supply Voltage Range
2.5V To 3.6V, 2.7V To 3.6V
Rohs Compliant
Yes
Access Time (max)
6ns
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Supply Current
15mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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28. Revision History
3500I–DFLASH–8/07
Revision Level – Release Date
A – September 2005
B – November 2005
C – January 2006
D – February 2006
E – May 2006
F – July 2006
G – August 2006
H – August 2006
I – August 2007
History
Initial Release
Added 2.5V - 3.6V operating range.
Changed t
Changed t
Changed t
Changed t
Added text, in “Programming the Configuration Register”, to indicate
that power cycling is required to switch to “power of 2” page size
after the opcode enable has been executed.
Added “Legacy Commands” table.
Changed part 2 of the device ID to 00H.
Added Legacy Status Register Read opcode 57H. This opcode is
supported on devices with date code 0636 and later.
Corrected typographical errors.
Added errata regarding Chip Erase.
Added t
Added additional text to “power of 2” binary page size option.
Removed SER/BYTE statement from SI and SO pin descriptions in
Table 2-1.
Changed t
Changed t
Changed t
SCKR
VCSL
PUW
DIS
V
VSCL
XFR
RDPD
from 8 ns to 6 ns max (2.7-volt device).
and t
from 8 ns to 6 ns max (2.7-volt device).
and t
from 10 ms to 20 ms max.
from 30 µs to 50 µs min.
from 50 µs to 70 µs.
from 30 µs to 35 µs.
SCKF
COMP
parameters to Table 18-4.
values from 400 µs to 200 µs.
AT45DB161D
51

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