AT24C64C-PU Atmel, AT24C64C-PU Datasheet - Page 6
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AT24C64C-PU
Manufacturer Part Number
AT24C64C-PU
Description
IC EEPROM 64KBIT 1MHZ 8DIP
Manufacturer
Atmel
Datasheet
1.AT24C32CN-SH-B.pdf
(28 pages)
Specifications of AT24C64C-PU
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
400kHz, 1MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT24C64C-PU
Manufacturer:
ATMEL
Quantity:
5 530
Company:
Part Number:
AT24C64C-PU
Manufacturer:
ATMEL
Quantity:
5 000
Part Number:
AT24C64C-PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
4. Device Operation
Figure 4-1.
6
SCL
SDA
AT24C32C/64C
Software Reset
Start bit
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (refer to Data Valid-
ity timing diagram). Data changes during SCL high periods will indicate a start or stop condition
as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (refer to
Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C32C/64C features a low power standby mode which is enabled:
a) upon power-up and b) after the receipt of the Stop bit and the completion of any internal
operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, and 2-wire
part can be protocol reset by following these steps:
(a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit
condition as shown below. The device is ready for next communication after above steps have
been completed.
1
2
Dummy Clock Cycles
3
8
9
Start bit
5298A–SEEPR–1/08
Stop bit