MT48H8M32LFB5-8 IT TR Micron Technology Inc, MT48H8M32LFB5-8 IT TR Datasheet - Page 35
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MT48H8M32LFB5-8 IT TR
Manufacturer Part Number
MT48H8M32LFB5-8 IT TR
Description
IC SDRAM 256MBIT 8NS 90VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT48V8M32LFB5-8_IT_TR.pdf
(75 pages)
Specifications of MT48H8M32LFB5-8 IT TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (8Mx32)
Speed
8ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1053-1
MT48H8M32LFB5-8 IT
MT48H8M32LFB5-8 IT
POWER-DOWN
DEEP POWER-DOWN
Figure 22: Terminating a WRITE Burst
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
Note:
Power-down occurs if CKE is registered low coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (64ms) since no REFRESH operations are performed in
this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data on the memory array will not
be retained once deep power-down mode is executed. Deep power-down mode is
entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH
at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep
power down.
DQMs are LOW.
COMMAND
ADDRESS
35
CLK
DQ
BANK,
WRITE
COL n
D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T0
n
IN
t
CKS). See Figure 24.
TERMINATE
BURST
T1
256Mb: x32 Mobile SDRAM
DON’T CARE
COMMAND
(ADDRESS)
(DATA)
T2
NEXT
©2003 Micron Technology, Inc. All rights reserved.
Operation