MT45W4MW16BCGB-701 WT Micron Technology Inc, MT45W4MW16BCGB-701 WT Datasheet - Page 14

• Manufacturer Part Number: MT45W4MW16BCGB-701 WT
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BCGB-701 WT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
Burst Mode READ (4-Word Burst)
Note:
(WRITE operations always use fixed latency). Variable latency allows the CellularRAM to
be configured for minimum latency at high clock frequencies, but the controller must
monitor WAIT to detect any conflict with refresh cycles.
Fixed latency outputs the first data word after the worst-case access delay, including
allowance for refresh collisions. The initial latency time and clock speed determine the
latency count setting. Fixed latency is used when the controller cannot monitor WAIT.
Fixed latency also provides improved performance at lower clock frequencies.
The WAIT output asserts when a burst is initiated and de-asserts to indicate when data is
to be transferred into or out of memory. WAIT will again be asserted at the boundary of
the 128-word row, unless wrapping within the burst length.
To access other devices on the same bus without the timing penalty of the initial latency
for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK.
CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst
is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise,
OE# can remain LOW. Note that the WAIT output will continue to be active and, as a
result, no other devices should directly share the WAIT connection to the controller. To
continue the burst sequence, OE# is taken LOW, and then CLK is restarted after valid
data is available on the bus.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than
CE# should be taken HIGH and the burst should be restarted with a new CE# LOW/ADV#
LOW cycle.
DQ[15:0]
LB#/UB#
A[21:0]
ADV#
WAIT
WE#
OE#
Nondefault BCR settings for burst mode READ (4-word burst): fixed or variable latency;
latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. Figure 8 is repre-
sentative of variable latency with no refresh collision or fixed-latency access.
CLK
CE#
t
CEM. If a burst suspension will cause CE# to remain LOW for longer than
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
READ burst identified
address
(WE# = HIGH)
Valid
Latency code 2 (3 clocks)
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D0
D1
Don’t Care
Bus Operating Modes
©2005 Micron Technology, Inc. All rights reserved.
D2
D3
Undefined
t
CEM,