MT46V16M8P-75:D TR Micron Technology Inc, MT46V16M8P-75:D TR Datasheet - Page 54

• Manufacturer Part Number: MT46V16M8P-75:D TR
• Description: IC DDR SDRAM 128MBIT 66TSOP
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M8P-75:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (16M x 8)
• Speed: 7.5ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Organization: 16Mx8
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 130mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 27:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
COMMAND
COMMAND
COMMAND
Nonconsecutive READ Bursts
ADDRESS
ADDRESS
ADDRESS
DQS
DQS
DQS
Notes:
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order follow-
5. Shown with nominal
Bank,
Bank,
Bank,
Col n
Col n
Col n
READ
READ
READ
T0
T0
T0
the first).
ing DO b.
CL = 2
NOP
NOP
NOP
T1
T1
T1
CL = 2.5
CL = 3
t
AC,
t
DQSCK, and
NOP
NOP
NOP
T2
T2
T2
54
DO
n
T2n
T2n
DO
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
t
DQSQ.
Bank,
Col b
Bank,
Bank,
Col b
Col b
READ
READ
READ
T3
T3
T3
DO
n
128Mb: x4, x8, x16 DDR SDRAM
T3n
T3n
T3n
DON’T CARE
T4
T4
T4
NOP
NOP
NOP
T4n
©2004 Micron Technology, Inc. All rights reserved.
TRANSITIONING DATA
T5
T5
T5
NOP
NOP
NOP
DO
b
Operations
T5n
T5n
DO
b
T6
T6
T6
NOP
NOP
NOP
DO
b