MT46V16M8P-75:D TR Micron Technology Inc, MT46V16M8P-75:D TR Datasheet - Page 59

• Manufacturer Part Number: MT46V16M8P-75:D TR
• Description: IC DDR SDRAM 128MBIT 66TSOP
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M8P-75:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (16M x 8)
• Speed: 7.5ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Organization: 16Mx8
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 130mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 32:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
COMMAND
ADDRESS
BA0, BA1
Case 1:
Case 2:
DQS
DQS
CK#
CKE
A10
DM
DQ
DQ
CK
t
t
AC (MIN) and
AC (MAX) and
Bank READ – Without Auto Precharge
Notes:
t
t
IS
NOP
IS
T0
t
1
t
IH
t
IH
DQSCK (MIN)
t
DQSCK (MAX)
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. The PRECHARGE command can only be applied at T5 if
4. Disable auto precharge.
5. “Don’t Care” if A10 is HIGH at T5.
6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in
7. Refer to Figure 33 on page 60, Figure 34 on page 61, and Figure 35 on page 62 for detailed
t
t
Bank x
times.
the programmed order.
DQS and DQ timing.
IS
IS
Row
Row
ACT
T1
t
t
IH
IH
t
CK
t
t RAS 3
t
RCD
RC
NOP
T2
1
t
CH
t
CL
Bank x
READ
t
4
IS
Col n
T3
2
t
t
IH
LZ (MIN)
59
CL = 2
NOP
T4
t
1
RPRE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
LZ (MIN)
t
RPRE
ALL BANKS
ONE BANK
Bank x
128Mb: x4, x8, x16 DDR SDRAM
PRE
T5
t
3
DO
DQSCK (MIN)
t
n
5
DQSCK (MAX)
t
AC (MIN)
DO
t
n
AC (MAX)
T5n
t
RAS (MIN) is met.
t
DON’T CARE
RP
NOP
T6
1
©2004 Micron Technology, Inc. All rights reserved.
t
HZ (MAX)
T6n
t
RPST
t
RPST
NOP
T7
TRANSITIONING DATA
1
Operations
Bank x
Row
Row
ACT
T8