MT46V64M8P-75:D Micron Technology Inc, MT46V64M8P-75:D Datasheet - Page 50

• Manufacturer Part Number: MT46V64M8P-75:D
• Description: IC DDR SDRAM 512MBIT 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V64M8P-75:D

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 7.5ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 32:
Operating Mode
Extended Mode Register
Output Drive Strength
DLL Enable/Disable
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
Speed
-6/-6T
-75E
-75Z
-5B
-75
CAS Latency
The normal operating mode is selected by issuing a LOAD MODE REGISTER command
with bits A7–An each set to zero and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing an LMR command with bits A7 and A9–An each set to zero, bit A8 set
to one, and bits A0–A6 set to the desired values. Although not required by the Micron
device, JEDEC specifications recommend that a LOAD MODE REGISTER command
resetting the DLL should always be followed by a LOAD MODE REGISTER command
selecting normal operating mode.
All other combinations of values for A7–An are reserved for future use and/or test
modes. Test modes and reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable and output drive strength.
These functions are controlled via the bits shown in Figure 25 on page 51. The extended
mode register is programmed via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is
programmed again or until the device loses power. The enabling of the DLL should
always be followed by an LMR command to the mode register (BA0/BA1 = 0) to reset the
DLL. The extended mode register must be loaded when all banks are idle and no bursts
are in progress, and the controller must wait the specified time before initiating any
subsequent operation. Violating either requirement could result in an unspecified oper-
ation.
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The x16
supports a programmable option for reduced drive. This option is intended for the
support of the lighter load and/or point-to-point environments. The selection of the
reduced drive strength will alter the DQ and DQS pins from SSTL_2, Class II drive
strength to a reduced drive strength, which is approximately 54 percent of the SSTL_2,
Class II drive strength.
When the part is running without the DLL enabled, device functionality may be altered.
The DLL must be enabled for normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation (when the device exits self refresh mode, the DLL
is enabled automatically). Anytime the DLL is enabled, 200 clock cycles with CKE HIGH
must occur before a READ command can be issued.
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 100
CL = 2
Allowable Operating Clock Frequency (MHz)
50
75 ≤ f ≤ 167
75 ≤ f ≤ 167
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
CL = 2.5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR SDRAM
©2000 Micron Technology, Inc. All rights reserved.
133 ≤ f ≤ 200
CL = 3
–
–
–
–
Operations