IS42S16400D-6T ISSI, Integrated Silicon Solution Inc, IS42S16400D-6T Datasheet - Page 33
![no-image](/images/manufacturer_photos/0/3/347/issi__integrated_silicon_solution_inc_sml.jpg)
IS42S16400D-6T
Manufacturer Part Number
IS42S16400D-6T
Description
IC SDRAM 64MBIT 166MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S16400D-7TL.pdf
(57 pages)
Specifications of IS42S16400D-6T
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (4M x 16)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S16400D-6TL
Manufacturer:
ISSI
Quantity:
300
Company:
Part Number:
IS42S16400D-6TL
Manufacturer:
Hynix
Quantity:
333
IS42S16400D
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/21/07
COMMAND
INTERNAL
ADDRESS
CLOCK
COMMAND
INTERNAL
CKE
ADDRESS
CLK
DQ
CLOCK
CKE
CLK
DQ
READ
BANK a,
COL n
T0
NOP
T0
NOP
T1
WRITE
BANK a,
COL n
D
T1
IN
n
NOP
T2
D
OUT
T2
n
T3
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH;
the internal clock and related operation will resume on the
subsequent positive clock edge.
D
T3
OUT
n+1
NOP
T4
D
NOP
IN
T4
n+1
NOP
D
T5
OUT
D
DON'T CARE
NOP
n+2
IN
T5
n+2
DON'T CARE
NOP
D
T6
OUT
n+3
33