MT48H16M16LFBF-75:G TR Micron Technology Inc, MT48H16M16LFBF-75:G TR Datasheet - Page 40

• Manufacturer Part Number: MT48H16M16LFBF-75:G TR
• Description: IC SDRAM 256MBIT 132MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H16M16LFBF-75:G TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 132MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 8/6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 80mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1326-2

Truth Tables
Table 6:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
CKE
H
H
L
L
n-1
CKE
H
H
Truth Table – CKE
Notes: 1–4
L
L
n
Notes: 1. CKE
Reading or writing
Deep power-down
Deep power-down
Current State
Clock suspend
Clock suspend
All banks idle
All banks idle
All banks idle
Power-down
Power-down
Self refresh
Self refresh
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once
7. After exiting clock suspend at clock edge n, the device will resume operation and recog-
8. Deep power-down is power savings feature of this Mobile SDRAM device. This command is
clock edge.
MAND
for clock edge n + 1 (provided that
is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occur-
ring during the
t
nize the next command at clock edge n + 1.
BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW.
XSR period.
n
is the logic state of CKE at clock edge n; CKE
n
.
n
is the command registered at clock edge n, and ACTION
t
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
XSR period. A minimum of two NOP commands must be provided during
See Table 8 on page 43
BURST TERMINATE
AUTO REFRESH
Command
VALID
40
X
X
X
X
X
X
n
t
CKS is met).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile SDRAM
Maintain deep power-down
n-1
Deep power-down entry
Maintain clock suspend
Exit deep power-down
Maintain power-down
was the state of CKE at the previous
Maintain self refresh
Clock suspend entry
Power-down entry
Exit clock suspend
Self refresh entry
Exit power-down
Exit self refresh
Action
©2006 Micron Technology, Inc. All rights reserved.
n
n
is a result of COM-
Truth Tables
Notes
8
5
8
6
7
8
t
XSR