CY7C1361A-100BGC Cypress Semiconductor Corp, CY7C1361A-100BGC Datasheet
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CY7C1361A-100BGC
Specifications of CY7C1361A-100BGC
Related parts for CY7C1361A-100BGC
CY7C1361A-100BGC Summary of contents
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... JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The TA package version does not offer the JTAG capability. The CY7C1361A and CY7C1363A operate from a +3.3V power supply. All inputs and outputs are LVTTL-compatible. 7C1361A-150 ...
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... BYTE d WRITE D Q ENABLE Input Register Address Register OUTPUT REGISTER CLR D Q Binary Counter & Logic [1] BYTE b WRITE D Q BYTE a WRITE D Q ENABLE Input Register Address Register OUTPUT REGISTER D Q CLR Binary Counter & Logic CY7C1361A CY7C1363A DQa,DQb DQc,DQd DQa,DQb Page ...
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... ZZ DQb 18 DQa 63 DQb 19 DQa 62 V CCQ CCQ DQb SS 22 DQa 59 DQb 23 DQa 58 DQb CCQ CCQ CY7C1361A CY7C1363A DQb 80 DQb 79 DQb CCQ DQb DQb 74 DQb 73 72 DQb CCQ 69 DQb DQb 100-pin TQFP Version ZZ 64 DQa 63 DQa CCQ DQa 59 DQa 58 DQa 57 DQa 56 ...
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... DQb DQb BWb ADV DQb V CLK DQb V BWE DQb MODE TMS TDI TCK CY7C1361A CY7C1363A CCQ DQb DQb SS V DQb DQb SS V DQb V SS CCQ BWb DQb DQb V DQb DQb CCQ V DQa DQa SS BWa DQa DQa V DQa V SS CCQ V DQa DQa ...
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... Linear Burst HIGH on this pin selects Interleaved Burst. ZZ Input- Sleep: This active HIGH input puts the device in Asynchronous low-power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). CY7C1361A CY7C1363A Pin Description Page ...
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... Write control and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock’s rising edge. CE Input- Chip Enable: This active LOW input is used to enable the Synchronous device and to gate ADSP. CY7C1361A CY7C1363A Pin Description Pin Description ...
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... A package version. V Supply Core Power Supply: +3.3V –5% and +10 Ground Ground: GND I/O Power Power Supply for the I/O circuitry CCQ Supply NC – No Connect: These signals are not internally connected. User can leave it floating or connect CY7C1361A CY7C1363A Pin Description Page ...
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... CY7C1361A CY7C1363A Second Third Fourth Address Address Address (internal) (internal) (internal) A...A01 A...A10 A...A11 A...A10 A...A11 A...A00 A...A11 A...A00 A...A01 A...A00 A...A01 A...A10 Write OE CLK L-H High L-H High L-H High L-H High L-H High L L-H High L L L-H High L-H ...
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... Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs for the duration of t Description Test Conditions ZZ > > V CY7C1361A CY7C1363A BWb BWc ...
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... The first column defines the bit’s position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name, the third column is the TQFP pin number, and the fourth column is the BGA bump number. CY7C1361A CY7C1363A ) ...
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... TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use. CY7C1361A CY7C1363A plus t ). The CS CH Page ...
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... The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05259 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram CY7C1361A CY7C1363A SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE- EXIT2-IR 1 UPDATE- [11] Page ...
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... I = 100 A OHC [13 8.0 mA OLT [13 8.0 mA OHT /2; undershoot: V (AC) < – 0.5V for t < t KHKH IL KHKH must not exceed V . Control input signals (such as R/W, ADV/LD) may not have pulse widths less than t CC CY7C1361A CY7C1363A 0 Selection Circuitry [12] Min. Max. 2 0.3 CC –0.3 0.8 – ...
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... CH 17. Test conditions are specified using the load in TAP AC test conditions. Document #: 38-05259 Rev. *C [16, 17] Over the Operating Range Description THTL t THTH t t MVTH THMX t DVTH t THDX t TLQV t TLQX CY7C1361A CY7C1363A Min. Max ALL INPUT PULSES 3.0V 1.5V 1.5 ns 1.5 ns (b) t ...
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... Do not use these instructions; they are reserved for future use. 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations. CY7C1361A CY7C1363A Description Reserved for revision number. Defines depth of 256K or 512K words. Defines width of x36 or x18 bits. ...
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... CY7C1361A CY7C1363A (continued) Signal Name TQFP Bump BWa 93 BWb 94 5G BWc 95 3G BWd 100 2A DQc 1 2D DQc 2 1E DQc 3 DQc 6 1G DQc 7 2H DQc 8 1D DQc 9 2E DQc 12 2G DQc DQd 18 2K DQd 19 DQd 22 2M DQd 23 1N DQd 24 2P DQd 25 1K ...
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... ADV 22 ADSP 23 ADSC BWE 26 GW Document #: 38-05259 Rev. *C Boundary Scan Order (512K × 18) Bit# Bump CY7C1361A CY7C1363A (continued) Signal Name TQFP Bump ID CLK BWa 93 BWb 100 DQb 8 1D DQb 9 DQb 12 2G DQb DQb 18 DQb 19 DQb 22 2M DQb 23 1N DQb 24 MODE Page ...
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... Device deselected; all inputs < > all inputs static Max. CLK frequency = 0 CC Description Test Conditions T = 25° MHz 3.3V CC pins should be no greater than 200 mV. CC < – 2.0V for t < CY7C1361A CY7C1363A Ambient [18] [19,20,21] Temperature 3.3V–5/ +10% – Min. Max. 2 2.0 1.7 –0.3 –0.3 – ...
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... CCQ V = 2.5V 4.5 CCQ [15, 23, 28] 0 [15, 23, 28] 3.5 [30] 1.5 [30] 0.5 is less than t and t is less than t KQHZ KQLZ OEHZ CY7C1361A CY7C1363A TQFP Typ 200us Vcctyp 90% Vccmin 10% 1 V/ns (c) (d) 133 MHz 117 MHz 100 MHz Min. Max. Min. Max. ...
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... For the X18 product, there are only BWa and BWb for byte Write control. Document #: 38-05259 Rev OEQ OELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ , and CE are active CY7C1361A CY7C1363A Q(A2+2) Q(A2+3) Q(A2) BURST READ is only available for A package version. 2 Page Q(A2+1) Q(A2 ...
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... CLK t S ADSP ADSC t S ADDRESS A1 t BWa, BWb, [31] [29] BWc, BWd, BWE GW [32] [30] CE ADV OE t KQX DQ Q SINGLE WRITE Document #: 38-05259 Rev OEHZ D(A1) D(A2) D(A2+2) BURST WRITE CY7C1361A CY7C1363A D(A2+2) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2) BURST WRITE Page ...
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... Read/Write Timing CLK t S ADSP ADSC ADDRESS A2 t BWa, BWb, [31] [29] BWc, BWd, BWE, GW [32] [30] CE ADV OE DQ Q(A1) Single Reads Document #: 38-05259 Rev Q(A2) D(A3) Single Write CY7C1361A CY7C1363A A5 Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) D(A5) Burst Read D(A5+1) Burst Write Page ...
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... Ordering Code 150 CY7C1361A-150AJC CY7C1361A-150AC CY7C1361A-150BGC 133 CY7C1361A-133AJC CY7C1361A-133AC CY7C1361A-133BGC 117 CY7C1361A-117AJC CY7C1361A-117AC CY7C1361A-117BGC 100 CY7C1361A-100AJC CY7C1361A-100AC CY7C1361A-100BGC Document #: 38-05259 Rev ZZS I (active Three-state Package Name A101 100-lead 1.4 mm Thin Quad Flat Pack A101 100-lead 1.4 mm Thin Quad Flat Pack BG119 119-ball BGA ( ...
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... CY7C1363A-133AC CY7C1363A-133BGC 117 CY7C1363A-117AJC CY7C1363A-117AC CY7C1363A-117BGC 100 CY7C1363A-100AJC CY7C1363A-100AC CY7C1363A-100BGC 133 CY7C1361A-133AJI CY7C1361A-133AI CY7C1361A-133BGI 117 CY7C1361A-117AJI CY7C1361A-117AI CY7C1361A-117BGI 100 CY7C1361A-100AJI CY7C1361A-100AI CY7C1361A-100BGI 133 CY7C1363A-133AJI CY7C1363A-133AI CY7C1363A-133BGI 117 CY7C1363A-117AJI CY7C1363A-117AI CY7C1363A-117BGI 100 CY7C1363A-100AJI CY7C1363A-100AI CY7C1363A-100BGI Document #: 38-05259 Rev. *C Package Name Package Type A101 100-lead ...
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... Package Diagrams 100-lead Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05259 Rev. *C CY7C1361A CY7C1363A 51-85050-*A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead BGA ( 2.4) BG119 CY7C1361A CY7C1363A 51-85115-*A ...
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... Document Title:CY7C1361A/CY7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Document Number: 38-05259 REV ECN No. Issue Date ** 113847 05/17/02 *A 116225 06/20/02 *B 117836 09/12/02 *C 123145 01/18/03 Document #: 38-05259 Rev. *C Orig. of Description of Change Change GLC New Data Sheet BRI Removed GVT part numbers from title and body of data sheet ...