CY7C1361A-100BGC Cypress Semiconductor Corp, CY7C1361A-100BGC Datasheet - Page 6

• Manufacturer Part Number: CY7C1361A-100BGC
• Description: IC SRAM 9MBIT 100MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361A-100BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1118

Document #: 38-05259 Rev. *C
256K × 36 Pin Descriptions
512K × 18 Pin Descriptions
(a) 6P, 7P, 7N, 6N, 6M,
(b) 7H, 6H, 7G, 6G, 6F,
(c) 2D, 1D, 1E, 2E, 2F,
(d) 1K, 2K, 1L, 2L, 2M,
3D, 5D, 3E, 5E, 3F, 5F,
1B, 7B, 1C, 7C, 4D, 3J,
5J, 4L, 1R, 5R, 7R, 1T,
6C, 2R, 6R, 2T, 3T, 5T,
1A, 7A, 1F, 7F, 1J, 7J,
5B, 6B, 2C, 3C, 5C,
3H, 5H, 3K, 5K, 3M,
2A, 3A, 5A, 6A, 3B,
5M, 3N, 5N, 3P, 5P
4C, 2J, 4J, 6J, 4R
X18 PBGA Pins
X36 PBGA Pins
6E, 7E, 7D, 6D,
1G, 2G, 1H, 2H,
1M, 7M, 1U, 7U
6L, 7L, 6K, 7K,
1N, 2N, 1P, 2P
2T, 6T, 6U
3G
4M
4P
4N
4H
4K
4E
6T
5L
2U
3U
4U
5U
35, 34, 33, 32, 100,
99, 82, 81, 80, 48,
47, 46, 45, 44, 49,
(c) 1, 2, 3, 6, 7, 8, 9,
40, 55, 60, 67, 71,
(a) 51, 52, 53, 56,
(b) 68, 69, 72, 73,
(d) 18, 19, 22, 23,
57, 58, 59, 62, 63
74, 75, 78, 79, 80
24, 25, 28, 29, 30
5, 10, 17, 21, 26,
4, 11, 20, 27, 54,
92 (AJ Version)
X18 QFP Pins
43 (A Version)
38, 39, 42 for A
X36 QFP Pins
for BG and AJ
for BG and AJ
15, 41, 65, 91
61, 70, 77
14, 16, 66
version
version
version
12, 13
76, 90
37
36
50
93
94
87
88
89
98
38
39
43
42
(continued)
Name
BWE
BWa
BWb
Name
CLK
V
GW
Pin
CE
DQa
DQb
DQd
TMS
TDO
DQc
TCK
A0
A1
V
V
Pin
TDI
NC
A
CCQ
CC
SS
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Power Supply Core Power Supply: +3.3V – 5% and +10%
I/O Power
Ground
Input-
Input-
Input-
Input-
Input-
Input-
Output
Supply
Type
Output
Input/
Type
Input
–
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
Byte Write Enables: A byte Write enable is LOW for a
Write cycle and HIGH for a Read cycle. BWa controls DQa.
BWb controls DQb. Data I/O are high impedance if either
of these inputs are LOW, conditioned by BWE being LOW.
Write Enable: This active LOW input gates byte Write
operations and must meet the set-up and hold times
around the rising edge of CLK.
Global Write: This active LOW input allows a full 18-bit
Write to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising
edge of CLK.
Clock: This signal registers the addresses, data, chip
enables, Write control and burst control inputs on its rising
edge. All synchronous inputs must meet set-up and hold
times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
Data Inputs/Outputs: First Byte is DQa. Second Byte is
DQb. Third Byte is DQc. Fourth Byte is DQd. Input data
must meet set-up and hold times around the rising edge
of CLK.
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not
available for A package version.
IEEE 1149.1 Test Output: LVTTL-level output. Not
available for A package version.
Ground: GND.
Power Supply for the I/O circuitry
No Connect: These signals are not internally connected.
User can leave it floating or connect it to V
Pin Description
Pin Description
CY7C1361A
CY7C1363A
CC
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or V
SS
.