CY7C138-25JC Cypress Semiconductor Corp, CY7C138-25JC Datasheet - Page 8

• Manufacturer Part Number: CY7C138-25JC
• Description: IC SRAM 32KBIT 25NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C138-25JC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 32K (4K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Density: 32Kb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 12b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 180mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Word Size: 8b
• Number Of Words: 4K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1445

Switching Waveforms
Notes
Document #: 38-06037 Rev. *E
20. BUSY = HIGH for the writing port.
21. CE
22. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
24. R/W must be HIGH during all address transitions.
SEM OR CE
SEM OR CE
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
placed on the bus for the required t
be as short as the specified t
DATA OUT
ADDRESS
DATA OUT
ADDRESS
L
DATA IN
DATA IN
= CE
R/W
R/W
OE
R
= LOW.
Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)
Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)
PWE
.
SD
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can
(continued)
t
SA
t
t
HZOE
SA
t
SCE
t
SCE
t
AW
t
HIGH IMPEDANCE
AW
t
HZWE
t
WC
t
WC
t
PWE
t
PWE
PWE
t
SD
DATA VALID
t
SD
or (t
HIGH IMPEDANCE
DATA VALID
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data to be
t
HD
t
t
HD
LZWE
t
HA
[22, 23, 24]
t
LZOE
[22, 24, 25]
t
CY7C138, CY7C139
HA
Page 8 of 17
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